Lines Matching +full:d +full:- +full:cache +full:- +full:sets
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/pinctrl/pads-imx8qm.h>
12 #include <dt-bindings/thermal/thermal.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
31 vpu-core0 = &vpu_core0;
32 vpu-core1 = &vpu_core1;
33 vpu-core2 = &vpu_core2;
37 #address-cells = <2>;
38 #size-cells = <0>;
40 cpu-map {
68 compatible = "arm,cortex-a53";
71 enable-method = "psci";
72 i-cache-size = <0x8000>;
73 i-cache-line-size = <64>;
74 i-cache-sets = <256>;
75 d-cache-size = <0x8000>;
76 d-cache-line-size = <64>;
77 d-cache-sets = <128>;
78 next-level-cache = <&A53_L2>;
79 operating-points-v2 = <&a53_opp_table>;
80 #cooling-cells = <2>;
85 compatible = "arm,cortex-a53";
88 enable-method = "psci";
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <256>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
94 d-cache-sets = <128>;
95 next-level-cache = <&A53_L2>;
96 operating-points-v2 = <&a53_opp_table>;
97 #cooling-cells = <2>;
102 compatible = "arm,cortex-a53";
105 enable-method = "psci";
106 i-cache-size = <0x8000>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <256>;
109 d-cache-size = <0x8000>;
110 d-cache-line-size = <64>;
111 d-cache-sets = <128>;
112 next-level-cache = <&A53_L2>;
113 operating-points-v2 = <&a53_opp_table>;
114 #cooling-cells = <2>;
119 compatible = "arm,cortex-a53";
122 enable-method = "psci";
123 i-cache-size = <0x8000>;
124 i-cache-line-size = <64>;
125 i-cache-sets = <256>;
126 d-cache-size = <0x8000>;
127 d-cache-line-size = <64>;
128 d-cache-sets = <128>;
129 next-level-cache = <&A53_L2>;
130 operating-points-v2 = <&a53_opp_table>;
131 #cooling-cells = <2>;
136 compatible = "arm,cortex-a72";
139 enable-method = "psci";
140 i-cache-size = <0xC000>;
141 i-cache-line-size = <64>;
142 i-cache-sets = <256>;
143 d-cache-size = <0x8000>;
144 d-cache-line-size = <64>;
145 d-cache-sets = <256>;
146 next-level-cache = <&A72_L2>;
147 operating-points-v2 = <&a72_opp_table>;
148 #cooling-cells = <2>;
153 compatible = "arm,cortex-a72";
156 enable-method = "psci";
157 next-level-cache = <&A72_L2>;
158 operating-points-v2 = <&a72_opp_table>;
159 #cooling-cells = <2>;
162 A53_L2: l2-cache0 {
163 compatible = "cache";
164 cache-level = <2>;
165 cache-unified;
166 cache-size = <0x100000>;
167 cache-line-size = <64>;
168 cache-sets = <1024>;
171 A72_L2: l2-cache1 {
172 compatible = "cache";
173 cache-level = <2>;
174 cache-unified;
175 cache-size = <0x100000>;
176 cache-line-size = <64>;
177 cache-sets = <1024>;
181 a53_opp_table: opp-table-0 {
182 compatible = "operating-points-v2";
183 opp-shared;
185 opp-600000000 {
186 opp-hz = /bits/ 64 <600000000>;
187 opp-microvolt = <900000>;
188 clock-latency-ns = <150000>;
191 opp-896000000 {
192 opp-hz = /bits/ 64 <896000000>;
193 opp-microvolt = <1000000>;
194 clock-latency-ns = <150000>;
197 opp-1104000000 {
198 opp-hz = /bits/ 64 <1104000000>;
199 opp-microvolt = <1100000>;
200 clock-latency-ns = <150000>;
203 opp-1200000000 {
204 opp-hz = /bits/ 64 <1200000000>;
205 opp-microvolt = <1100000>;
206 clock-latency-ns = <150000>;
207 opp-suspend;
211 a72_opp_table: opp-table-1 {
212 compatible = "operating-points-v2";
213 opp-shared;
215 opp-600000000 {
216 opp-hz = /bits/ 64 <600000000>;
217 opp-microvolt = <1000000>;
218 clock-latency-ns = <150000>;
221 opp-1056000000 {
222 opp-hz = /bits/ 64 <1056000000>;
223 opp-microvolt = <1000000>;
224 clock-latency-ns = <150000>;
227 opp-1296000000 {
228 opp-hz = /bits/ 64 <1296000000>;
229 opp-microvolt = <1100000>;
230 clock-latency-ns = <150000>;
233 opp-1596000000 {
234 opp-hz = /bits/ 64 <1596000000>;
235 opp-microvolt = <1100000>;
236 clock-latency-ns = <150000>;
237 opp-suspend;
241 gic: interrupt-controller@51a00000 {
242 compatible = "arm,gic-v3";
248 #interrupt-cells = <3>;
249 interrupt-controller;
251 interrupt-parent = <&gic>;
255 compatible = "arm,armv8-pmuv3";
260 compatible = "arm,psci-1.0";
265 compatible = "arm,armv8-timer";
267 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
273 compatible = "arm,mmu-500";
274 interrupt-parent = <&gic>;
276 #global-interrupts = <1>;
277 #iommu-cells = <2>;
313 system-controller {
314 compatible = "fsl,imx-scu";
315 mbox-names = "tx0",
322 pd: power-controller {
323 compatible = "fsl,imx8qm-scu-pd", "fsl,scu-pd";
324 #power-domain-cells = <1>;
327 clk: clock-controller {
328 compatible = "fsl,imx8qm-clk", "fsl,scu-clk";
329 #clock-cells = <2>;
333 compatible = "fsl,imx8qm-iomuxc";
336 scu_reset: reset-controller {
337 compatible = "fsl,imx-scu-reset";
338 #reset-cells = <1>;
342 compatible = "fsl,imx8qxp-sc-rtc";
346 compatible = "fsl,imx8qm-scu-ocotp";
347 #address-cells = <1>;
348 #size-cells = <1>;
349 read-only;
360 tsens: thermal-sensor {
361 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
362 #thermal-sensor-cells = <1>;
366 compatible = "fsl,imx8qm-sc-wdt", "fsl,imx-sc-wdt";
367 timeout-sec = <60>;
371 thermal-zones {
372 cpu0-thermal {
373 polling-delay-passive = <250>;
374 polling-delay = <2000>;
375 thermal-sensors = <&tsens IMX_SC_R_A53>;
391 cooling-maps {
394 cooling-device =
403 cpu1-thermal {
404 polling-delay-passive = <250>;
405 polling-delay = <2000>;
406 thermal-sensors = <&tsens IMX_SC_R_A72>;
422 cooling-maps {
425 cooling-device =
432 gpu0-thermal {
433 polling-delay-passive = <250>;
434 polling-delay = <2000>;
435 thermal-sensors = <&tsens IMX_SC_R_GPU_0_PID0>;
452 gpu1-thermal {
453 polling-delay-passive = <250>;
454 polling-delay = <2000>;
455 thermal-sensors = <&tsens IMX_SC_R_GPU_1_PID0>;
472 drc0-thermal {
473 polling-delay-passive = <250>;
474 polling-delay = <2000>;
475 thermal-sensors = <&tsens IMX_SC_R_DRC_0>;
493 clk_dummy: clock-dummy {
494 compatible = "fixed-clock";
495 #clock-cells = <0>;
496 clock-frequency = <0>;
497 clock-output-names = "clk_dummy";
500 clk_esai1_rx_clk: clock-esai1-rx {
501 compatible = "fixed-clock";
502 #clock-cells = <0>;
503 clock-frequency = <0>;
504 clock-output-names = "esai1_rx_clk";
507 clk_esai1_rx_hf_clk: clock-esai1-rx-hf {
508 compatible = "fixed-clock";
509 #clock-cells = <0>;
510 clock-frequency = <0>;
511 clock-output-names = "esai1_rx_hf_clk";
514 clk_esai1_tx_clk: clock-esai1-tx {
515 compatible = "fixed-clock";
516 #clock-cells = <0>;
517 clock-frequency = <0>;
518 clock-output-names = "esai1_tx_clk";
521 clk_esai1_tx_hf_clk: clock-esai1-tx-hf {
522 compatible = "fixed-clock";
523 #clock-cells = <0>;
524 clock-frequency = <0>;
525 clock-output-names = "esai1_tx_hf_clk";
528 clk_hdmi_rx_mclk: clock-hdmi-rx-mclk {
529 compatible = "fixed-clock";
530 #clock-cells = <0>;
531 clock-frequency = <0>;
532 clock-output-names = "hdmi-rx-mclk";
535 clk_mlb_clk: clock-mlb-clk {
536 compatible = "fixed-clock";
537 #clock-cells = <0>;
538 clock-frequency = <0>;
539 clock-output-names = "mlb_clk";
542 clk_sai5_rx_bclk: clock-sai5-rx-bclk {
543 compatible = "fixed-clock";
544 #clock-cells = <0>;
545 clock-frequency = <0>;
546 clock-output-names = "sai5_rx_bclk";
549 clk_sai5_tx_bclk: clock-sai5-tx-bclk {
550 compatible = "fixed-clock";
551 #clock-cells = <0>;
552 clock-frequency = <0>;
553 clock-output-names = "sai5_tx_bclk";
556 clk_sai6_rx_bclk: clock-sai6-rx-bclk {
557 compatible = "fixed-clock";
558 #clock-cells = <0>;
559 clock-frequency = <0>;
560 clock-output-names = "sai6_rx_bclk";
563 clk_sai6_tx_bclk: clock-sai6-tx-bclk {
564 compatible = "fixed-clock";
565 #clock-cells = <0>;
566 clock-frequency = <0>;
567 clock-output-names = "sai6_tx_bclk";
570 clk_spdif1_rx: clock-spdif1-rx {
571 compatible = "fixed-clock";
572 #clock-cells = <0>;
573 clock-frequency = <0>;
574 clock-output-names = "spdif1_rx";
577 lvds_ipg_clk: clock-controller-lvds-ipg {
578 compatible = "fixed-clock";
579 #clock-cells = <0>;
580 clock-frequency = <24000000>;
581 clock-output-names = "lvds0_ipg_clk";
584 dsi_ipg_clk: clock-controller-dsi-ipg {
585 compatible = "fixed-clock";
586 #clock-cells = <0>;
587 clock-frequency = <120000000>;
588 clock-output-names = "dsi_ipg_clk";
591 mipi_pll_div2_clk: clock-controller-mipi-div2-pll {
592 compatible = "fixed-clock";
593 #clock-cells = <0>;
594 clock-frequency = <432000000>;
595 clock-output-names = "mipi_pll_div2_clk";
599 compatible = "simple-bus";
600 #address-cells = <1>;
601 #size-cells = <1>;
605 compatible = "fsl,imx8qm-hifi4";
610 clock-names = "ipg", "ocram", "core";
611 power-domains = <&pd IMX_SC_R_MU_13B>,
618 mbox-names = "tx", "rx", "rxdb";
619 firmware-name = "imx/dsp/hifi4.bin";
625 #include "imx8-ss-security.dtsi"
626 #include "imx8-ss-cm41.dtsi"
627 #include "imx8-ss-audio.dtsi"
628 #include "imx8-ss-vpu.dtsi"
629 #include "imx8-ss-gpu0.dtsi"
630 #include "imx8-ss-mipi0.dtsi"
631 #include "imx8-ss-lvds0.dtsi"
632 #include "imx8-ss-mipi1.dtsi"
633 #include "imx8-ss-lvds1.dtsi"
634 #include "imx8-ss-img.dtsi"
635 #include "imx8-ss-dma.dtsi"
636 #include "imx8-ss-conn.dtsi"
637 #include "imx8-ss-lsio.dtsi"
638 #include "imx8-ss-hsio.dtsi"
641 #include "imx8qm-ss-img.dtsi"
642 #include "imx8qm-ss-dma.dtsi"
643 #include "imx8qm-ss-conn.dtsi"
644 #include "imx8qm-ss-lsio.dtsi"
645 #include "imx8qm-ss-audio.dtsi"
646 #include "imx8qm-ss-lvds.dtsi"
647 #include "imx8qm-ss-mipi.dtsi"
648 #include "imx8qm-ss-hsio.dtsi"
650 /delete-node/ &dsp;