Lines Matching +full:0 +full:x88000
38 #size-cells = <0>;
66 A53_0: cpu@0 {
69 reg = <0x0 0x0>;
72 i-cache-size = <0x8000>;
75 d-cache-size = <0x8000>;
86 reg = <0x0 0x1>;
89 i-cache-size = <0x8000>;
92 d-cache-size = <0x8000>;
103 reg = <0x0 0x2>;
106 i-cache-size = <0x8000>;
109 d-cache-size = <0x8000>;
120 reg = <0x0 0x3>;
123 i-cache-size = <0x8000>;
126 d-cache-size = <0x8000>;
137 reg = <0x0 0x100>;
140 i-cache-size = <0xC000>;
143 d-cache-size = <0x8000>;
154 reg = <0x0 0x101>;
166 cache-size = <0x100000>;
175 cache-size = <0x100000>;
181 a53_opp_table: opp-table-0 {
243 reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */
244 <0x0 0x51b00000 0 0xC0000>, /* GICR */
245 <0x0 0x52000000 0 0x2000>, /* GICC */
246 <0x0 0x52010000 0 0x1000>, /* GICH */
247 <0x0 0x52020000 0 0x20000>; /* GICV */
275 reg = <0 0x51400000 0 0x40000>;
318 mboxes = <&lsio_mu1 0 0
319 &lsio_mu1 1 0
347 reg = <0x1c4 6>;
351 reg = <0x1c6 6>;
485 #clock-cells = <0>;
486 clock-frequency = <0>;
492 #clock-cells = <0>;
493 clock-frequency = <0>;
499 #clock-cells = <0>;
500 clock-frequency = <0>;
506 #clock-cells = <0>;
507 clock-frequency = <0>;
513 #clock-cells = <0>;
514 clock-frequency = <0>;
520 #clock-cells = <0>;
521 clock-frequency = <0>;
527 #clock-cells = <0>;
528 clock-frequency = <0>;
534 #clock-cells = <0>;
535 clock-frequency = <0>;
541 #clock-cells = <0>;
542 clock-frequency = <0>;
548 #clock-cells = <0>;
549 clock-frequency = <0>;
555 #clock-cells = <0>;
556 clock-frequency = <0>;
562 #clock-cells = <0>;
563 clock-frequency = <0>;
569 #clock-cells = <0>;
576 #clock-cells = <0>;
583 #clock-cells = <0>;
592 ranges = <0x55000000 0x0 0x55000000 0x1000000>;
596 reg = <0x556e8000 0x88000>;
605 mboxes = <&lsio_mu13 0 0>,
606 <&lsio_mu13 1 0>,
607 <&lsio_mu13 3 0>;