Lines Matching +full:phy +full:- +full:output +full:- +full:clock

1 // SPDX-License-Identifier: GPL-2.0+
8 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
16 compatible = "fsl,imx8q-pcie";
19 reg-names = "dbi", "config";
22 #interrupt-cells = <1>;
24 interrupt-names = "msi";
25 #address-cells = <3>;
26 #size-cells = <2>;
30 clock-names = "dbi", "mstr", "slv";
31 bus-range = <0x00 0xff>;
33 interrupt-map = <0 0 0 1 &gic 0 73 4>,
37 interrupt-map-mask = <0 0 0 0x7>;
38 num-lanes = <1>;
39 num-viewport = <4>;
40 power-domains = <&pd IMX_SC_R_PCIE_A>;
41 fsl,max-link-speed = <3>;
45 pcie0_ep: pciea_ep: pcie-ep@5f000000 {
46 compatible = "fsl,imx8q-pcie-ep";
49 reg-names = "dbi", "addr_space";
50 num-lanes = <1>;
52 interrupt-names = "dma";
56 clock-names = "dbi", "mstr", "slv";
57 power-domains = <&pd IMX_SC_R_PCIE_A>;
58 fsl,max-link-speed = <3>;
59 num-ib-windows = <6>;
60 num-ob-windows = <6>;
65 compatible = "fsl,imx8q-pcie";
68 reg-names = "dbi", "config";
71 #interrupt-cells = <1>;
74 interrupt-names = "msi", "dma";
75 #address-cells = <3>;
76 #size-cells = <2>;
80 clock-names = "dbi", "mstr", "slv";
81 bus-range = <0x00 0xff>;
83 interrupt-map = <0 0 0 1 &gic 0 105 4>,
87 interrupt-map-mask = <0 0 0 0x7>;
88 num-lanes = <1>;
89 num-viewport = <4>;
90 power-domains = <&pd IMX_SC_R_PCIE_B>;
91 fsl,max-link-speed = <3>;
96 compatible = "fsl,imx8qm-ahci";
101 clock-names = "sata", "sata_ref";
102 phy-names = "sata-phy", "cali-phy0", "cali-phy1";
103 power-domains = <&pd IMX_SC_R_SATA_0>;
105 * Since "REXT" pin is only present for first lane PHY
107 * by the PHY used by SATA.
110 * the third lane PHY is used by SATA.
118 pciea_lpcg: clock-controller@5f050000 {
119 compatible = "fsl,imx8qxp-lpcg";
122 #clock-cells = <1>;
123 clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>, <IMX_LPCG_CLK_6>;
124 clock-output-names = "hsio_pciea_mstr_axi_clk",
127 power-domains = <&pd IMX_SC_R_PCIE_A>;
130 sata_lpcg: clock-controller@5f070000 {
131 compatible = "fsl,imx8qxp-lpcg";
134 #clock-cells = <1>;
135 clock-indices = <IMX_LPCG_CLK_4>;
136 clock-output-names = "hsio_sata_clk";
137 power-domains = <&pd IMX_SC_R_SATA_0>;
140 phyx2_lpcg: clock-controller@5f080000 {
141 compatible = "fsl,imx8qxp-lpcg";
145 #clock-cells = <1>;
146 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
148 clock-output-names = "hsio_phyx2_pclk_0",
152 power-domains = <&pd IMX_SC_R_SERDES_0>;
155 phyx1_lpcg: clock-controller@5f090000 {
156 compatible = "fsl,imx8qxp-lpcg";
160 #clock-cells = <1>;
161 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
163 clock-output-names = "hsio_phyx1_pclk",
167 power-domains = <&pd IMX_SC_R_SERDES_1>;
170 phyx2_crr0_lpcg: clock-controller@5f0a0000 {
171 compatible = "fsl,imx8qxp-lpcg";
174 #clock-cells = <1>;
175 clock-indices = <IMX_LPCG_CLK_4>;
176 clock-output-names = "hsio_phyx2_per_clk";
177 power-domains = <&pd IMX_SC_R_SERDES_0>;
180 pciea_crr2_lpcg: clock-controller@5f0c0000 {
181 compatible = "fsl,imx8qxp-lpcg";
184 #clock-cells = <1>;
185 clock-indices = <IMX_LPCG_CLK_4>;
186 clock-output-names = "hsio_pciea_per_clk";
187 power-domains = <&pd IMX_SC_R_PCIE_A>;
190 sata_crr4_lpcg: clock-controller@5f0e0000 {
191 compatible = "fsl,imx8qxp-lpcg";
194 #clock-cells = <1>;
195 clock-indices = <IMX_LPCG_CLK_4>;
196 clock-output-names = "hsio_sata_per_clk";
197 power-domains = <&pd IMX_SC_R_SATA_0>;
200 hsio_phy: phy@5f180000 {
201 compatible = "fsl,imx8qm-hsio";
206 reg-names = "reg", "phy", "ctrl", "misc";
221 clock-names = "pclk0", "pclk1", "apb_pclk0", "apb_pclk1",
225 #phy-cells = <3>;
226 power-domains = <&pd IMX_SC_R_SERDES_0>, <&pd IMX_SC_R_SERDES_1>;