Lines Matching +full:imx7ulp +full:- +full:lpi2c

1 // SPDX-License-Identifier: GPL-2.0+
3  * Copyright 2018-2019 NXP
8 	uart4_lpcg: clock-controller@5a4a0000 {
9 		compatible = "fsl,imx8qxp-lpcg";
11 		#clock-cells = <1>;
14 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
15 		clock-output-names = "uart4_lpcg_baud_clk",
17 		power-domains = <&pd IMX_SC_R_UART_4>;
21 		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
24 		interrupt-parent = <&gic>;
27 		clock-names = "per", "ipg";
28 		assigned-clocks = <&clk IMX_SC_R_I2C_4 IMX_SC_PM_CLK_PER>;
29 		assigned-clock-rates = <24000000>;
30 		power-domains = <&pd IMX_SC_R_I2C_4>;
34 	i2c4_lpcg: clock-controller@5ac40000 {
35 		compatible = "fsl,imx8qxp-lpcg";
37 		#clock-cells = <1>;
40 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
41 		clock-output-names = "i2c4_lpcg_clk",
43 		power-domains = <&pd IMX_SC_R_I2C_4>;
46 	can1_lpcg: clock-controller@5ace0000 {
47 		compatible = "fsl,imx8qxp-lpcg";
49 		#clock-cells = <1>;
52 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
53 		clock-output-names = "can1_lpcg_pe_clk",
56 		power-domains = <&pd IMX_SC_R_CAN_1>;
59 	can2_lpcg: clock-controller@5acf0000 {
60 		compatible = "fsl,imx8qxp-lpcg";
62 		#clock-cells = <1>;
65 		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
66 		clock-output-names = "can2_lpcg_pe_clk",
69 		power-domains = <&pd IMX_SC_R_CAN_2>;
75 	#dma-cells = <3>;
76 	dma-channels = <22>;
77 	dma-channel-mask = <0xf00>;
100 	power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
128 	dma-channels = <10>;
139 	power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
152 	fsl,clk-source = /bits/ 8 <1>;
158 	assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>;
159 	fsl,clk-source = /bits/ 8 <1>;
165 	assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>;
166 	fsl,clk-source = /bits/ 8 <1>;
170 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
172 	dma-names = "rx","tx";
176 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
178 	dma-names = "rx","tx";
182 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
184 	dma-names = "rx","tx";
188 	compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
190 	dma-names = "rx","tx";
194 	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
198 	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
202 	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
206 	compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";