Lines Matching +full:opp +full:- +full:1300000000
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interconnect/imx8mq.h>
15 #include "imx8mq-pinfunc.h"
18 interrupt-parent = <&gpc>;
20 #address-cells = <2>;
21 #size-cells = <2>;
45 ckil: clock-ckil {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <32768>;
49 clock-output-names = "ckil";
52 osc_25m: clock-osc-25m {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <25000000>;
56 clock-output-names = "osc_25m";
59 osc_27m: clock-osc-27m {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <27000000>;
63 clock-output-names = "osc_27m";
66 hdmi_phy_27m: clock-hdmi-phy-27m {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <27000000>;
70 clock-output-names = "hdmi_phy_27m";
73 clk_ext1: clock-ext1 {
74 compatible = "fixed-clock";
75 #clock-cells = <0>;
76 clock-frequency = <133000000>;
77 clock-output-names = "clk_ext1";
80 clk_ext2: clock-ext2 {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <133000000>;
84 clock-output-names = "clk_ext2";
87 clk_ext3: clock-ext3 {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <133000000>;
91 clock-output-names = "clk_ext3";
94 clk_ext4: clock-ext4 {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <133000000>;
98 clock-output-names = "clk_ext4";
102 #address-cells = <1>;
103 #size-cells = <0>;
107 compatible = "arm,cortex-a53";
109 clock-latency = <61036>; /* two CLK32 periods */
111 enable-method = "psci";
112 i-cache-size = <0x8000>;
113 i-cache-line-size = <64>;
114 i-cache-sets = <256>;
115 d-cache-size = <0x8000>;
116 d-cache-line-size = <64>;
117 d-cache-sets = <128>;
118 next-level-cache = <&A53_L2>;
119 operating-points-v2 = <&a53_opp_table>;
120 #cooling-cells = <2>;
121 nvmem-cells = <&cpu_speed_grade>;
122 nvmem-cell-names = "speed_grade";
127 compatible = "arm,cortex-a53";
129 clock-latency = <61036>; /* two CLK32 periods */
131 enable-method = "psci";
132 i-cache-size = <0x8000>;
133 i-cache-line-size = <64>;
134 i-cache-sets = <256>;
135 d-cache-size = <0x8000>;
136 d-cache-line-size = <64>;
137 d-cache-sets = <128>;
138 next-level-cache = <&A53_L2>;
139 operating-points-v2 = <&a53_opp_table>;
140 #cooling-cells = <2>;
145 compatible = "arm,cortex-a53";
147 clock-latency = <61036>; /* two CLK32 periods */
149 enable-method = "psci";
150 i-cache-size = <0x8000>;
151 i-cache-line-size = <64>;
152 i-cache-sets = <256>;
153 d-cache-size = <0x8000>;
154 d-cache-line-size = <64>;
155 d-cache-sets = <128>;
156 next-level-cache = <&A53_L2>;
157 operating-points-v2 = <&a53_opp_table>;
158 #cooling-cells = <2>;
163 compatible = "arm,cortex-a53";
165 clock-latency = <61036>; /* two CLK32 periods */
167 enable-method = "psci";
168 i-cache-size = <0x8000>;
169 i-cache-line-size = <64>;
170 i-cache-sets = <256>;
171 d-cache-size = <0x8000>;
172 d-cache-line-size = <64>;
173 d-cache-sets = <128>;
174 next-level-cache = <&A53_L2>;
175 operating-points-v2 = <&a53_opp_table>;
176 #cooling-cells = <2>;
179 A53_L2: l2-cache0 {
181 cache-level = <2>;
182 cache-unified;
183 cache-size = <0x100000>;
184 cache-line-size = <64>;
185 cache-sets = <1024>;
189 a53_opp_table: opp-table {
190 compatible = "operating-points-v2";
191 opp-shared;
193 opp-800000000 {
194 opp-hz = /bits/ 64 <800000000>;
195 opp-microvolt = <900000>;
197 opp-supported-hw = <0xf>, <0x4>;
198 clock-latency-ns = <150000>;
199 opp-suspend;
202 opp-1000000000 {
203 opp-hz = /bits/ 64 <1000000000>;
204 opp-microvolt = <900000>;
206 opp-supported-hw = <0xe>, <0x3>;
207 clock-latency-ns = <150000>;
208 opp-suspend;
211 opp-1300000000 {
212 opp-hz = /bits/ 64 <1300000000>;
213 opp-microvolt = <1000000>;
214 opp-supported-hw = <0xc>, <0x4>;
215 clock-latency-ns = <150000>;
216 opp-suspend;
219 opp-1500000000 {
220 opp-hz = /bits/ 64 <1500000000>;
221 opp-microvolt = <1000000>;
222 opp-supported-hw = <0x8>, <0x3>;
223 clock-latency-ns = <150000>;
224 opp-suspend;
230 * non-configurable funnel don't show up on the AMBA
233 compatible = "arm,coresight-static-funnel";
235 in-ports {
236 #address-cells = <1>;
237 #size-cells = <0>;
243 remote-endpoint = <&etm0_out_port>;
251 remote-endpoint = <&etm1_out_port>;
259 remote-endpoint = <&etm2_out_port>;
267 remote-endpoint = <&etm3_out_port>;
272 out-ports {
275 remote-endpoint = <&hugo_funnel_in_port0>;
282 compatible = "arm,cortex-a53-pmu";
284 interrupt-parent = <&gic>;
288 compatible = "arm,psci-1.0";
292 thermal-zones {
293 cpu_thermal: cpu-thermal {
294 polling-delay-passive = <250>;
295 polling-delay = <2000>;
296 thermal-sensors = <&tmu 0>;
299 cpu_alert: cpu-alert {
305 cpu-crit {
312 cooling-maps {
315 cooling-device =
324 gpu-thermal {
325 polling-delay-passive = <250>;
326 polling-delay = <2000>;
327 thermal-sensors = <&tmu 1>;
330 gpu_alert: gpu-alert {
336 gpu-crit {
343 cooling-maps {
346 cooling-device =
352 vpu-thermal {
353 polling-delay-passive = <250>;
354 polling-delay = <2000>;
355 thermal-sensors = <&tmu 2>;
358 vpu-crit {
368 compatible = "arm,armv8-timer";
370 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
373 interrupt-parent = <&gic>;
374 arm,no-tick-in-suspend;
378 compatible = "fsl,imx8mq-soc", "simple-bus";
379 #address-cells = <1>;
380 #size-cells = <1>;
382 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
383 nvmem-cells = <&imx8mq_uid>;
384 nvmem-cell-names = "soc_unique_id";
387 compatible = "arm,coresight-etm4x", "arm,primecell";
391 clock-names = "apb_pclk";
393 out-ports {
396 remote-endpoint = <&ca_funnel_in_port0>;
403 compatible = "arm,coresight-etm4x", "arm,primecell";
407 clock-names = "apb_pclk";
409 out-ports {
412 remote-endpoint = <&ca_funnel_in_port1>;
419 compatible = "arm,coresight-etm4x", "arm,primecell";
423 clock-names = "apb_pclk";
425 out-ports {
428 remote-endpoint = <&ca_funnel_in_port2>;
435 compatible = "arm,coresight-etm4x", "arm,primecell";
439 clock-names = "apb_pclk";
441 out-ports {
444 remote-endpoint = <&ca_funnel_in_port3>;
451 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
454 clock-names = "apb_pclk";
456 in-ports {
457 #address-cells = <1>;
458 #size-cells = <0>;
464 remote-endpoint = <&ca_funnel_out_port0>;
478 out-ports {
481 remote-endpoint = <&etf_in_port>;
488 compatible = "arm,coresight-tmc", "arm,primecell";
491 clock-names = "apb_pclk";
493 in-ports {
496 remote-endpoint = <&hugo_funnel_out_port0>;
501 out-ports {
504 remote-endpoint = <&etr_in_port>;
511 compatible = "arm,coresight-tmc", "arm,primecell";
514 clock-names = "apb_pclk";
516 in-ports {
519 remote-endpoint = <&etf_out_port>;
526 compatible = "fsl,aips-bus", "simple-bus";
528 #address-cells = <1>;
529 #size-cells = <1>;
533 #sound-dai-cells = <0>;
534 compatible = "fsl,imx8mq-sai";
540 clock-names = "bus", "mclk1", "mclk2", "mclk3";
542 dma-names = "rx", "tx";
547 #sound-dai-cells = <0>;
548 compatible = "fsl,imx8mq-sai";
554 clock-names = "bus", "mclk1", "mclk2", "mclk3";
556 dma-names = "rx", "tx";
561 #sound-dai-cells = <0>;
562 compatible = "fsl,imx8mq-sai";
568 clock-names = "bus", "mclk1", "mclk2", "mclk3";
570 dma-names = "rx", "tx";
575 #sound-dai-cells = <0>;
576 compatible = "fsl,imx8mq-sai";
582 clock-names = "bus", "mclk1", "mclk2", "mclk3";
584 dma-names = "rx", "tx";
589 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
594 gpio-controller;
595 #gpio-cells = <2>;
596 interrupt-controller;
597 #interrupt-cells = <2>;
598 gpio-ranges = <&iomuxc 0 10 30>;
602 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
607 gpio-controller;
608 #gpio-cells = <2>;
609 interrupt-controller;
610 #interrupt-cells = <2>;
611 gpio-ranges = <&iomuxc 0 40 21>;
615 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
620 gpio-controller;
621 #gpio-cells = <2>;
622 interrupt-controller;
623 #interrupt-cells = <2>;
624 gpio-ranges = <&iomuxc 0 61 26>;
628 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
633 gpio-controller;
634 #gpio-cells = <2>;
635 interrupt-controller;
636 #interrupt-cells = <2>;
637 gpio-ranges = <&iomuxc 0 87 32>;
641 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
646 gpio-controller;
647 #gpio-cells = <2>;
648 interrupt-controller;
649 #interrupt-cells = <2>;
650 gpio-ranges = <&iomuxc 0 119 30>;
654 compatible = "fsl,imx8mq-tmu";
658 little-endian;
659 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
660 fsl,tmu-calibration = <0x00000000 0x00000023>,
703 #thermal-sensor-cells = <1>;
707 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
715 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
723 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
730 sdma2: dma-controller@302c0000 {
731 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
736 clock-names = "ipg", "ahb";
737 #dma-cells = <3>;
738 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
741 lcdif: lcd-controller@30320000 {
742 compatible = "fsl,imx8mq-lcdif", "fsl,imx6sx-lcdif";
748 clock-names = "pix", "axi", "disp_axi";
749 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
753 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
756 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
761 remote-endpoint = <&mipi_dsi_lcdif_in>;
767 compatible = "fsl,imx8mq-iomuxc";
772 compatible = "fsl,imx8mq-iomuxc-gpr", "syscon", "simple-mfd";
775 mux: mux-controller {
776 compatible = "mmio-mux";
777 #mux-control-cells = <1>;
778 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
783 compatible = "fsl,imx8mq-ocotp", "syscon";
786 #address-cells = <1>;
787 #size-cells = <1>;
802 imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */
806 cpu_speed_grade: speed-grade@10 { /* 0x440 */
810 fec_mac_address: mac-address@90 { /* 0x640 */
815 anatop: clock-controller@30360000 {
816 compatible = "fsl,imx8mq-anatop";
819 #clock-cells = <1>;
823 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
826 snvs_rtc: snvs-rtc-lp {
827 compatible = "fsl,sec-v4.0-mon-rtc-lp";
833 clock-names = "snvs-rtc";
836 snvs_pwrkey: snvs-powerkey {
837 compatible = "fsl,sec-v4.0-pwrkey";
841 clock-names = "snvs-pwrkey";
843 wakeup-source;
848 clk: clock-controller@30380000 {
849 compatible = "fsl,imx8mq-ccm";
853 #clock-cells = <1>;
857 clock-names = "ckil", "osc_25m", "osc_27m",
860 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
868 assigned-clock-rates = <0>, <0>,
875 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
883 src: reset-controller@30390000 {
884 compatible = "fsl,imx8mq-src", "syscon";
887 #reset-cells = <1>;
891 compatible = "fsl,imx8mq-gpc";
894 interrupt-parent = <&gic>;
895 interrupt-controller;
896 #interrupt-cells = <3>;
899 #address-cells = <1>;
900 #size-cells = <0>;
902 pgc_mipi: power-domain@0 {
903 #power-domain-cells = <0>;
922 pgc_pcie: power-domain@1 {
923 #power-domain-cells = <0>;
925 power-domains = <&pgc_pcie2>;
928 pgc_otg1: power-domain@2 {
929 #power-domain-cells = <0>;
933 pgc_otg2: power-domain@3 {
934 #power-domain-cells = <0>;
938 pgc_ddr1: power-domain@4 {
939 #power-domain-cells = <0>;
943 pgc_gpu: power-domain@5 {
944 #power-domain-cells = <0>;
952 pgc_vpu: power-domain@6 {
953 #power-domain-cells = <0>;
958 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
962 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
966 assigned-clock-rates = <600000000>,
972 pgc_disp: power-domain@7 {
973 #power-domain-cells = <0>;
977 pgc_mipi_csi1: power-domain@8 {
978 #power-domain-cells = <0>;
982 pgc_mipi_csi2: power-domain@9 {
983 #power-domain-cells = <0>;
987 pgc_pcie2: power-domain@a {
988 #power-domain-cells = <0>;
996 compatible = "fsl,aips-bus", "simple-bus";
998 #address-cells = <1>;
999 #size-cells = <1>;
1003 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
1008 clock-names = "ipg", "per";
1009 #pwm-cells = <3>;
1014 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
1019 clock-names = "ipg", "per";
1020 #pwm-cells = <3>;
1025 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
1030 clock-names = "ipg", "per";
1031 #pwm-cells = <3>;
1036 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
1041 clock-names = "ipg", "per";
1042 #pwm-cells = <3>;
1047 compatible = "nxp,sysctr-timer";
1051 clock-names = "per";
1056 compatible = "fsl,aips-bus", "simple-bus";
1058 #address-cells = <1>;
1059 #size-cells = <1>;
1064 compatible = "fsl,imx35-spdif";
1077 clock-names = "core", "rxtx0",
1083 dma-names = "rx", "tx";
1088 #address-cells = <1>;
1089 #size-cells = <0>;
1090 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
1095 clock-names = "ipg", "per";
1097 dma-names = "rx", "tx";
1102 #address-cells = <1>;
1103 #size-cells = <0>;
1104 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
1109 clock-names = "ipg", "per";
1111 dma-names = "rx", "tx";
1116 #address-cells = <1>;
1117 #size-cells = <0>;
1118 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
1123 clock-names = "ipg", "per";
1125 dma-names = "rx", "tx";
1130 compatible = "fsl,imx8mq-uart",
1131 "fsl,imx6q-uart";
1136 clock-names = "ipg", "per";
1138 dma-names = "rx", "tx";
1143 compatible = "fsl,imx8mq-uart",
1144 "fsl,imx6q-uart";
1149 clock-names = "ipg", "per";
1151 dma-names = "rx", "tx";
1156 compatible = "fsl,imx8mq-uart",
1157 "fsl,imx6q-uart";
1162 clock-names = "ipg", "per";
1164 dma-names = "rx", "tx";
1169 compatible = "fsl,imx35-spdif";
1182 clock-names = "core", "rxtx0",
1188 dma-names = "rx", "tx";
1193 #sound-dai-cells = <0>;
1194 compatible = "fsl,imx8mq-sai";
1200 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1202 dma-names = "rx", "tx";
1207 #sound-dai-cells = <0>;
1208 compatible = "fsl,imx8mq-sai";
1214 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1216 dma-names = "rx", "tx";
1221 compatible = "fsl,sec-v4.0";
1222 #address-cells = <1>;
1223 #size-cells = <1>;
1229 clock-names = "aclk", "ipg";
1232 compatible = "fsl,sec-v4.0-job-ring";
1239 compatible = "fsl,sec-v4.0-job-ring";
1245 compatible = "fsl,sec-v4.0-job-ring";
1252 compatible = "fsl,imx8mq-nwl-dsi";
1254 #address-cells = <1>;
1255 #size-cells = <0>;
1261 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
1262 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
1265 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
1267 assigned-clock-rates = <80000000>, <266000000>, <20000000>;
1269 mux-controls = <&mux 0>;
1270 power-domains = <&pgc_mipi>;
1272 phy-names = "dphy";
1277 reset-names = "byte", "dpi", "esc", "pclk";
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1286 #address-cells = <1>;
1287 #size-cells = <0>;
1290 remote-endpoint = <&lcdif_mipi_dsi>;
1304 compatible = "fsl,imx8mq-mipi-dphy";
1307 clock-names = "phy_ref";
1308 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
1312 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
1315 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
1316 #phy-cells = <0>;
1317 power-domains = <&pgc_mipi>;
1322 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1326 #address-cells = <1>;
1327 #size-cells = <0>;
1332 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1336 #address-cells = <1>;
1337 #size-cells = <0>;
1342 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1346 #address-cells = <1>;
1347 #size-cells = <0>;
1352 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1356 #address-cells = <1>;
1357 #size-cells = <0>;
1362 compatible = "fsl,imx8mq-uart",
1363 "fsl,imx6q-uart";
1368 clock-names = "ipg", "per";
1370 dma-names = "rx", "tx";
1375 compatible = "fsl,imx8mq-mipi-csi2";
1380 clock-names = "core", "esc", "ui";
1381 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
1384 assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1385 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1388 power-domains = <&pgc_mipi_csi1>;
1392 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
1394 interconnect-names = "dram";
1398 #address-cells = <1>;
1399 #size-cells = <0>;
1405 remote-endpoint = <&csi1_ep>;
1412 compatible = "fsl,imx8mq-csi";
1416 clock-names = "mclk";
1421 remote-endpoint = <&csi1_mipi_ep>;
1427 compatible = "fsl,imx8mq-mipi-csi2";
1432 clock-names = "core", "esc", "ui";
1433 assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
1436 assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1437 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1440 power-domains = <&pgc_mipi_csi2>;
1444 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
1446 interconnect-names = "dram";
1450 #address-cells = <1>;
1451 #size-cells = <0>;
1457 remote-endpoint = <&csi2_ep>;
1464 compatible = "fsl,imx8mq-csi";
1468 clock-names = "mclk";
1473 remote-endpoint = <&csi2_mipi_ep>;
1479 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
1483 #mbox-cells = <2>;
1487 compatible = "fsl,imx8mq-usdhc",
1488 "fsl,imx7d-usdhc";
1494 clock-names = "ipg", "ahb", "per";
1495 fsl,tuning-start-tap = <20>;
1496 fsl,tuning-step = <2>;
1497 bus-width = <4>;
1502 compatible = "fsl,imx8mq-usdhc",
1503 "fsl,imx7d-usdhc";
1509 clock-names = "ipg", "ahb", "per";
1510 fsl,tuning-start-tap = <20>;
1511 fsl,tuning-step = <2>;
1512 bus-width = <4>;
1517 #address-cells = <1>;
1518 #size-cells = <0>;
1519 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
1522 reg-names = "QuadSPI", "QuadSPI-memory";
1526 clock-names = "qspi_en", "qspi";
1530 sdma1: dma-controller@30bd0000 {
1531 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
1536 clock-names = "ipg", "ahb";
1537 #dma-cells = <3>;
1538 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1542 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1553 clock-names = "ipg", "ahb", "ptp",
1555 assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
1559 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1563 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1564 fsl,num-tx-queues = <3>;
1565 fsl,num-rx-queues = <3>;
1566 nvmem-cells = <&fec_mac_address>;
1567 nvmem-cell-names = "mac-address";
1568 fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
1574 compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc";
1578 #interconnect-cells = <1>;
1579 operating-points-v2 = <&noc_opp_table>;
1581 noc_opp_table: opp-table {
1582 compatible = "operating-points-v2";
1584 opp-133000000 {
1585 opp-hz = /bits/ 64 <133333333>;
1588 opp-400000000 {
1589 opp-hz = /bits/ 64 <400000000>;
1592 opp-800000000 {
1593 opp-hz = /bits/ 64 <800000000>;
1599 compatible = "fsl,aips-bus", "simple-bus";
1601 #address-cells = <1>;
1602 #size-cells = <1>;
1605 irqsteer: interrupt-controller@32e2d000 {
1606 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
1610 clock-names = "ipg";
1612 fsl,num-irqs = <64>;
1613 interrupt-controller;
1614 #interrupt-cells = <1>;
1626 clock-names = "core", "shader", "bus", "reg";
1627 #cooling-cells = <2>;
1628 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
1633 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
1638 assigned-clock-rates = <800000000>, <800000000>,
1640 power-domains = <&pgc_gpu>;
1644 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1649 clock-names = "bus_early", "ref", "suspend";
1650 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1652 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1654 assigned-clock-rates = <500000000>, <100000000>;
1657 phy-names = "usb2-phy", "usb3-phy";
1658 power-domains = <&pgc_otg1>;
1659 snps,parkmode-disable-ss-quirk;
1663 usb3_phy0: usb-phy@381f0040 {
1664 compatible = "fsl,imx8mq-usb-phy";
1667 clock-names = "phy";
1668 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1669 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1670 assigned-clock-rates = <100000000>;
1671 #phy-cells = <0>;
1676 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1681 clock-names = "bus_early", "ref", "suspend";
1682 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1684 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1686 assigned-clock-rates = <500000000>, <100000000>;
1689 phy-names = "usb2-phy", "usb3-phy";
1690 power-domains = <&pgc_otg2>;
1691 snps,parkmode-disable-ss-quirk;
1695 usb3_phy1: usb-phy@382f0040 {
1696 compatible = "fsl,imx8mq-usb-phy";
1699 clock-names = "phy";
1700 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1701 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1702 assigned-clock-rates = <100000000>;
1703 #phy-cells = <0>;
1707 vpu_g1: video-codec@38300000 {
1708 compatible = "nxp,imx8mq-vpu-g1";
1712 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
1715 vpu_g2: video-codec@38310000 {
1716 compatible = "nxp,imx8mq-vpu-g2";
1720 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
1723 vpu_blk_ctrl: blk-ctrl@38320000 {
1724 compatible = "fsl,imx8mq-vpu-blk-ctrl";
1726 power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
1727 power-domain-names = "bus", "g1", "g2";
1730 clock-names = "g1", "g2";
1731 #power-domain-cells = <1>;
1735 compatible = "fsl,imx8mq-pcie";
1738 reg-names = "dbi", "config";
1739 #address-cells = <3>;
1740 #size-cells = <2>;
1742 bus-range = <0x00 0xff>;
1744 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1745 num-lanes = <1>;
1747 interrupt-names = "msi";
1748 #interrupt-cells = <1>;
1749 interrupt-map-mask = <0 0 0 0x7>;
1750 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1754 fsl,max-link-speed = <2>;
1755 linux,pci-domain = <0>;
1760 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1761 power-domains = <&pgc_pcie>;
1765 reset-names = "pciephy", "apps", "turnoff";
1766 assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
1769 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1772 assigned-clock-rates = <250000000>, <100000000>,
1778 compatible = "fsl,imx8mq-pcie";
1781 reg-names = "dbi", "config";
1782 #address-cells = <3>;
1783 #size-cells = <2>;
1785 bus-range = <0x00 0xff>;
1787 <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1788 num-lanes = <1>;
1790 interrupt-names = "msi";
1791 #interrupt-cells = <1>;
1792 interrupt-map-mask = <0 0 0 0x7>;
1793 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1797 fsl,max-link-speed = <2>;
1798 linux,pci-domain = <1>;
1803 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1804 power-domains = <&pgc_pcie>;
1808 reset-names = "pciephy", "apps", "turnoff";
1809 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
1812 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1815 assigned-clock-rates = <250000000>, <100000000>,
1820 pcie1_ep: pcie-ep@33c00000 {
1821 compatible = "fsl,imx8mq-pcie-ep";
1824 reg-names = "dbi", "addr_space";
1825 num-lanes = <1>;
1827 interrupt-names = "dma";
1828 fsl,max-link-speed = <2>;
1833 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1834 power-domains = <&pgc_pcie>;
1838 reset-names = "pciephy", "apps", "turnoff";
1839 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
1842 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1845 assigned-clock-rates = <250000000>, <100000000>,
1847 num-ib-windows = <4>;
1848 num-ob-windows = <4>;
1852 gic: interrupt-controller@38800000 {
1853 compatible = "arm,gic-v3";
1859 #interrupt-cells = <3>;
1860 interrupt-controller;
1862 interrupt-parent = <&gic>;
1865 ddrc: memory-controller@3d400000 {
1866 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
1868 clock-names = "core", "pll", "alt", "apb";
1876 ddr-pmu@3d800000 {
1877 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1879 interrupt-parent = <&gic>;