Lines Matching +full:imx8mq +full:- +full:sdma
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
7 #include <dt-bindings/clock/imx8mq-clock.h>
8 #include <dt-bindings/power/imx8mq-power.h>
9 #include <dt-bindings/reset/imx8mq-reset.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include "dt-bindings/input/input.h"
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
14 #include <dt-bindings/interconnect/imx8mq.h>
15 #include "imx8mq-pinfunc.h"
18 interrupt-parent = <&gpc>;
20 #address-cells = <2>;
21 #size-cells = <2>;
45 ckil: clock-ckil {
46 compatible = "fixed-clock";
47 #clock-cells = <0>;
48 clock-frequency = <32768>;
49 clock-output-names = "ckil";
52 osc_25m: clock-osc-25m {
53 compatible = "fixed-clock";
54 #clock-cells = <0>;
55 clock-frequency = <25000000>;
56 clock-output-names = "osc_25m";
59 osc_27m: clock-osc-27m {
60 compatible = "fixed-clock";
61 #clock-cells = <0>;
62 clock-frequency = <27000000>;
63 clock-output-names = "osc_27m";
66 hdmi_phy_27m: clock-hdmi-phy-27m {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <27000000>;
70 clock-output-names = "hdmi_phy_27m";
73 clk_ext1: clock-ext1 {
74 compatible = "fixed-clock";
75 #clock-cells = <0>;
76 clock-frequency = <133000000>;
77 clock-output-names = "clk_ext1";
80 clk_ext2: clock-ext2 {
81 compatible = "fixed-clock";
82 #clock-cells = <0>;
83 clock-frequency = <133000000>;
84 clock-output-names = "clk_ext2";
87 clk_ext3: clock-ext3 {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <133000000>;
91 clock-output-names = "clk_ext3";
94 clk_ext4: clock-ext4 {
95 compatible = "fixed-clock";
96 #clock-cells = <0>;
97 clock-frequency = <133000000>;
98 clock-output-names = "clk_ext4";
102 #address-cells = <1>;
103 #size-cells = <0>;
107 compatible = "arm,cortex-a53";
110 enable-method = "psci";
111 i-cache-size = <0x8000>;
112 i-cache-line-size = <64>;
113 i-cache-sets = <256>;
114 d-cache-size = <0x8000>;
115 d-cache-line-size = <64>;
116 d-cache-sets = <128>;
117 next-level-cache = <&A53_L2>;
118 operating-points-v2 = <&a53_opp_table>;
119 #cooling-cells = <2>;
120 nvmem-cells = <&cpu_speed_grade>;
121 nvmem-cell-names = "speed_grade";
126 compatible = "arm,cortex-a53";
129 enable-method = "psci";
130 i-cache-size = <0x8000>;
131 i-cache-line-size = <64>;
132 i-cache-sets = <256>;
133 d-cache-size = <0x8000>;
134 d-cache-line-size = <64>;
135 d-cache-sets = <128>;
136 next-level-cache = <&A53_L2>;
137 operating-points-v2 = <&a53_opp_table>;
138 #cooling-cells = <2>;
143 compatible = "arm,cortex-a53";
146 enable-method = "psci";
147 i-cache-size = <0x8000>;
148 i-cache-line-size = <64>;
149 i-cache-sets = <256>;
150 d-cache-size = <0x8000>;
151 d-cache-line-size = <64>;
152 d-cache-sets = <128>;
153 next-level-cache = <&A53_L2>;
154 operating-points-v2 = <&a53_opp_table>;
155 #cooling-cells = <2>;
160 compatible = "arm,cortex-a53";
163 enable-method = "psci";
164 i-cache-size = <0x8000>;
165 i-cache-line-size = <64>;
166 i-cache-sets = <256>;
167 d-cache-size = <0x8000>;
168 d-cache-line-size = <64>;
169 d-cache-sets = <128>;
170 next-level-cache = <&A53_L2>;
171 operating-points-v2 = <&a53_opp_table>;
172 #cooling-cells = <2>;
175 A53_L2: l2-cache0 {
177 cache-level = <2>;
178 cache-unified;
179 cache-size = <0x100000>;
180 cache-line-size = <64>;
181 cache-sets = <1024>;
185 a53_opp_table: opp-table {
186 compatible = "operating-points-v2";
187 opp-shared;
189 opp-800000000 {
190 opp-hz = /bits/ 64 <800000000>;
191 opp-microvolt = <900000>;
193 opp-supported-hw = <0xf>, <0x4>;
194 clock-latency-ns = <150000>;
195 opp-suspend;
198 opp-1000000000 {
199 opp-hz = /bits/ 64 <1000000000>;
200 opp-microvolt = <900000>;
202 opp-supported-hw = <0xe>, <0x3>;
203 clock-latency-ns = <150000>;
204 opp-suspend;
207 opp-1300000000 {
208 opp-hz = /bits/ 64 <1300000000>;
209 opp-microvolt = <1000000>;
210 opp-supported-hw = <0xc>, <0x4>;
211 clock-latency-ns = <150000>;
212 opp-suspend;
215 opp-1500000000 {
216 opp-hz = /bits/ 64 <1500000000>;
217 opp-microvolt = <1000000>;
218 opp-supported-hw = <0x8>, <0x3>;
219 clock-latency-ns = <150000>;
220 opp-suspend;
226 * non-configurable funnel don't show up on the AMBA
229 compatible = "arm,coresight-static-funnel";
231 in-ports {
232 #address-cells = <1>;
233 #size-cells = <0>;
239 remote-endpoint = <&etm0_out_port>;
247 remote-endpoint = <&etm1_out_port>;
255 remote-endpoint = <&etm2_out_port>;
263 remote-endpoint = <&etm3_out_port>;
268 out-ports {
271 remote-endpoint = <&hugo_funnel_in_port0>;
278 compatible = "arm,cortex-a53-pmu";
280 interrupt-parent = <&gic>;
284 compatible = "arm,psci-1.0";
288 thermal-zones {
289 cpu_thermal: cpu-thermal {
290 polling-delay-passive = <250>;
291 polling-delay = <2000>;
292 thermal-sensors = <&tmu 0>;
295 cpu_alert: cpu-alert {
301 cpu-crit {
308 cooling-maps {
311 cooling-device =
320 gpu-thermal {
321 polling-delay-passive = <250>;
322 polling-delay = <2000>;
323 thermal-sensors = <&tmu 1>;
326 gpu_alert: gpu-alert {
332 gpu-crit {
339 cooling-maps {
342 cooling-device =
348 vpu-thermal {
349 polling-delay-passive = <250>;
350 polling-delay = <2000>;
351 thermal-sensors = <&tmu 2>;
354 vpu-crit {
364 compatible = "arm,armv8-timer";
366 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
369 interrupt-parent = <&gic>;
370 arm,no-tick-in-suspend;
374 compatible = "fsl,imx8mq-soc", "simple-bus";
375 #address-cells = <1>;
376 #size-cells = <1>;
378 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
379 nvmem-cells = <&imx8mq_uid>;
380 nvmem-cell-names = "soc_unique_id";
383 compatible = "arm,coresight-etm4x", "arm,primecell";
387 clock-names = "apb_pclk";
389 out-ports {
392 remote-endpoint = <&ca_funnel_in_port0>;
399 compatible = "arm,coresight-etm4x", "arm,primecell";
403 clock-names = "apb_pclk";
405 out-ports {
408 remote-endpoint = <&ca_funnel_in_port1>;
415 compatible = "arm,coresight-etm4x", "arm,primecell";
419 clock-names = "apb_pclk";
421 out-ports {
424 remote-endpoint = <&ca_funnel_in_port2>;
431 compatible = "arm,coresight-etm4x", "arm,primecell";
435 clock-names = "apb_pclk";
437 out-ports {
440 remote-endpoint = <&ca_funnel_in_port3>;
447 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
450 clock-names = "apb_pclk";
452 in-ports {
453 #address-cells = <1>;
454 #size-cells = <0>;
460 remote-endpoint = <&ca_funnel_out_port0>;
474 out-ports {
477 remote-endpoint = <&etf_in_port>;
484 compatible = "arm,coresight-tmc", "arm,primecell";
487 clock-names = "apb_pclk";
489 in-ports {
492 remote-endpoint = <&hugo_funnel_out_port0>;
497 out-ports {
500 remote-endpoint = <&etr_in_port>;
507 compatible = "arm,coresight-tmc", "arm,primecell";
510 clock-names = "apb_pclk";
512 in-ports {
515 remote-endpoint = <&etf_out_port>;
522 compatible = "fsl,aips-bus", "simple-bus";
524 #address-cells = <1>;
525 #size-cells = <1>;
529 #sound-dai-cells = <0>;
530 compatible = "fsl,imx8mq-sai";
536 clock-names = "bus", "mclk1", "mclk2", "mclk3";
538 dma-names = "rx", "tx";
543 #sound-dai-cells = <0>;
544 compatible = "fsl,imx8mq-sai";
550 clock-names = "bus", "mclk1", "mclk2", "mclk3";
552 dma-names = "rx", "tx";
557 #sound-dai-cells = <0>;
558 compatible = "fsl,imx8mq-sai";
564 clock-names = "bus", "mclk1", "mclk2", "mclk3";
566 dma-names = "rx", "tx";
571 #sound-dai-cells = <0>;
572 compatible = "fsl,imx8mq-sai";
578 clock-names = "bus", "mclk1", "mclk2", "mclk3";
580 dma-names = "rx", "tx";
585 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
590 gpio-controller;
591 #gpio-cells = <2>;
592 interrupt-controller;
593 #interrupt-cells = <2>;
594 gpio-ranges = <&iomuxc 0 10 30>;
598 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
603 gpio-controller;
604 #gpio-cells = <2>;
605 interrupt-controller;
606 #interrupt-cells = <2>;
607 gpio-ranges = <&iomuxc 0 40 21>;
611 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
616 gpio-controller;
617 #gpio-cells = <2>;
618 interrupt-controller;
619 #interrupt-cells = <2>;
620 gpio-ranges = <&iomuxc 0 61 26>;
624 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
629 gpio-controller;
630 #gpio-cells = <2>;
631 interrupt-controller;
632 #interrupt-cells = <2>;
633 gpio-ranges = <&iomuxc 0 87 32>;
637 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
642 gpio-controller;
643 #gpio-cells = <2>;
644 interrupt-controller;
645 #interrupt-cells = <2>;
646 gpio-ranges = <&iomuxc 0 119 30>;
650 compatible = "fsl,imx8mq-tmu";
654 little-endian;
655 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
656 fsl,tmu-calibration = <0x00000000 0x00000023>,
699 #thermal-sensor-cells = <1>;
703 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
711 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
719 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt";
726 sdma2: dma-controller@302c0000 {
727 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
732 clock-names = "ipg", "ahb";
733 #dma-cells = <3>;
734 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
737 lcdif: lcd-controller@30320000 {
738 compatible = "fsl,imx8mq-lcdif", "fsl,imx6sx-lcdif";
744 clock-names = "pix", "axi", "disp_axi";
745 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
749 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
752 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
757 remote-endpoint = <&mipi_dsi_lcdif_in>;
763 compatible = "fsl,imx8mq-iomuxc";
768 compatible = "fsl,imx8mq-iomuxc-gpr", "syscon", "simple-mfd";
771 mux: mux-controller {
772 compatible = "mmio-mux";
773 #mux-control-cells = <1>;
774 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
779 compatible = "fsl,imx8mq-ocotp", "syscon";
782 #address-cells = <1>;
783 #size-cells = <1>;
798 imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */
802 cpu_speed_grade: speed-grade@10 { /* 0x440 */
806 fec_mac_address: mac-address@90 { /* 0x640 */
811 anatop: clock-controller@30360000 {
812 compatible = "fsl,imx8mq-anatop";
815 #clock-cells = <1>;
819 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
822 snvs_rtc: snvs-rtc-lp {
823 compatible = "fsl,sec-v4.0-mon-rtc-lp";
829 clock-names = "snvs-rtc";
832 snvs_pwrkey: snvs-powerkey {
833 compatible = "fsl,sec-v4.0-pwrkey";
837 clock-names = "snvs-pwrkey";
839 wakeup-source;
844 clk: clock-controller@30380000 {
845 compatible = "fsl,imx8mq-ccm";
849 #clock-cells = <1>;
853 clock-names = "ckil", "osc_25m", "osc_27m",
856 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>,
864 assigned-clock-rates = <0>, <0>,
871 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>,
879 src: reset-controller@30390000 {
880 compatible = "fsl,imx8mq-src", "syscon";
883 #reset-cells = <1>;
887 compatible = "fsl,imx8mq-gpc";
890 interrupt-parent = <&gic>;
891 interrupt-controller;
892 #interrupt-cells = <3>;
895 #address-cells = <1>;
896 #size-cells = <0>;
898 pgc_mipi: power-domain@0 {
899 #power-domain-cells = <0>;
918 pgc_pcie: power-domain@1 {
919 #power-domain-cells = <0>;
921 power-domains = <&pgc_pcie2>;
924 pgc_otg1: power-domain@2 {
925 #power-domain-cells = <0>;
929 pgc_otg2: power-domain@3 {
930 #power-domain-cells = <0>;
934 pgc_ddr1: power-domain@4 {
935 #power-domain-cells = <0>;
939 pgc_gpu: power-domain@5 {
940 #power-domain-cells = <0>;
948 pgc_vpu: power-domain@6 {
949 #power-domain-cells = <0>;
954 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>,
958 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>,
962 assigned-clock-rates = <600000000>,
968 pgc_disp: power-domain@7 {
969 #power-domain-cells = <0>;
973 pgc_mipi_csi1: power-domain@8 {
974 #power-domain-cells = <0>;
978 pgc_mipi_csi2: power-domain@9 {
979 #power-domain-cells = <0>;
983 pgc_pcie2: power-domain@a {
984 #power-domain-cells = <0>;
992 compatible = "fsl,aips-bus", "simple-bus";
994 #address-cells = <1>;
995 #size-cells = <1>;
999 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
1004 clock-names = "ipg", "per";
1005 #pwm-cells = <3>;
1010 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
1015 clock-names = "ipg", "per";
1016 #pwm-cells = <3>;
1021 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
1026 clock-names = "ipg", "per";
1027 #pwm-cells = <3>;
1032 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm";
1037 clock-names = "ipg", "per";
1038 #pwm-cells = <3>;
1043 compatible = "nxp,sysctr-timer";
1047 clock-names = "per";
1052 compatible = "fsl,aips-bus", "simple-bus";
1054 #address-cells = <1>;
1055 #size-cells = <1>;
1060 compatible = "fsl,imx35-spdif";
1073 clock-names = "core", "rxtx0",
1079 dma-names = "rx", "tx";
1084 #address-cells = <1>;
1085 #size-cells = <0>;
1086 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
1091 clock-names = "ipg", "per";
1093 dma-names = "rx", "tx";
1098 #address-cells = <1>;
1099 #size-cells = <0>;
1100 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
1105 clock-names = "ipg", "per";
1107 dma-names = "rx", "tx";
1112 #address-cells = <1>;
1113 #size-cells = <0>;
1114 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi";
1119 clock-names = "ipg", "per";
1121 dma-names = "rx", "tx";
1126 compatible = "fsl,imx8mq-uart",
1127 "fsl,imx6q-uart";
1132 clock-names = "ipg", "per";
1134 dma-names = "rx", "tx";
1139 compatible = "fsl,imx8mq-uart",
1140 "fsl,imx6q-uart";
1145 clock-names = "ipg", "per";
1147 dma-names = "rx", "tx";
1152 compatible = "fsl,imx8mq-uart",
1153 "fsl,imx6q-uart";
1158 clock-names = "ipg", "per";
1160 dma-names = "rx", "tx";
1165 compatible = "fsl,imx35-spdif";
1178 clock-names = "core", "rxtx0",
1184 dma-names = "rx", "tx";
1189 #sound-dai-cells = <0>;
1190 compatible = "fsl,imx8mq-sai";
1196 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1198 dma-names = "rx", "tx";
1203 #sound-dai-cells = <0>;
1204 compatible = "fsl,imx8mq-sai";
1210 clock-names = "bus", "mclk1", "mclk2", "mclk3";
1212 dma-names = "rx", "tx";
1217 compatible = "fsl,sec-v4.0";
1218 #address-cells = <1>;
1219 #size-cells = <1>;
1225 clock-names = "aclk", "ipg";
1228 compatible = "fsl,sec-v4.0-job-ring";
1235 compatible = "fsl,sec-v4.0-job-ring";
1241 compatible = "fsl,sec-v4.0-job-ring";
1248 compatible = "fsl,imx8mq-nwl-dsi";
1250 #address-cells = <1>;
1251 #size-cells = <0>;
1257 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
1258 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
1261 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
1263 assigned-clock-rates = <80000000>, <266000000>, <20000000>;
1265 mux-controls = <&mux 0>;
1266 power-domains = <&pgc_mipi>;
1268 phy-names = "dphy";
1273 reset-names = "byte", "dpi", "esc", "pclk";
1277 #address-cells = <1>;
1278 #size-cells = <0>;
1282 #address-cells = <1>;
1283 #size-cells = <0>;
1286 remote-endpoint = <&lcdif_mipi_dsi>;
1300 compatible = "fsl,imx8mq-mipi-dphy";
1303 clock-names = "phy_ref";
1304 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,
1308 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
1311 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
1312 #phy-cells = <0>;
1313 power-domains = <&pgc_mipi>;
1318 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1322 #address-cells = <1>;
1323 #size-cells = <0>;
1328 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1332 #address-cells = <1>;
1333 #size-cells = <0>;
1338 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1342 #address-cells = <1>;
1343 #size-cells = <0>;
1348 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
1352 #address-cells = <1>;
1353 #size-cells = <0>;
1358 compatible = "fsl,imx8mq-uart",
1359 "fsl,imx6q-uart";
1364 clock-names = "ipg", "per";
1366 dma-names = "rx", "tx";
1371 compatible = "fsl,imx8mq-mipi-csi2";
1376 clock-names = "core", "esc", "ui";
1377 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
1380 assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1381 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1384 power-domains = <&pgc_mipi_csi1>;
1388 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
1390 interconnect-names = "dram";
1394 #address-cells = <1>;
1395 #size-cells = <0>;
1401 remote-endpoint = <&csi1_ep>;
1408 compatible = "fsl,imx8mq-csi";
1412 clock-names = "mclk";
1417 remote-endpoint = <&csi1_mipi_ep>;
1423 compatible = "fsl,imx8mq-mipi-csi2";
1428 clock-names = "core", "esc", "ui";
1429 assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>,
1432 assigned-clock-rates = <266000000>, <333000000>, <66000000>;
1433 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1436 power-domains = <&pgc_mipi_csi2>;
1440 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
1442 interconnect-names = "dram";
1446 #address-cells = <1>;
1447 #size-cells = <0>;
1453 remote-endpoint = <&csi2_ep>;
1460 compatible = "fsl,imx8mq-csi";
1464 clock-names = "mclk";
1469 remote-endpoint = <&csi2_mipi_ep>;
1475 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
1479 #mbox-cells = <2>;
1483 compatible = "fsl,imx8mq-usdhc",
1484 "fsl,imx7d-usdhc";
1490 clock-names = "ipg", "ahb", "per";
1491 fsl,tuning-start-tap = <20>;
1492 fsl,tuning-step = <2>;
1493 bus-width = <4>;
1498 compatible = "fsl,imx8mq-usdhc",
1499 "fsl,imx7d-usdhc";
1505 clock-names = "ipg", "ahb", "per";
1506 fsl,tuning-start-tap = <20>;
1507 fsl,tuning-step = <2>;
1508 bus-width = <4>;
1513 #address-cells = <1>;
1514 #size-cells = <0>;
1515 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi";
1518 reg-names = "QuadSPI", "QuadSPI-memory";
1522 clock-names = "qspi_en", "qspi";
1526 sdma1: dma-controller@30bd0000 {
1527 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma";
1532 clock-names = "ipg", "ahb";
1533 #dma-cells = <3>;
1534 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1538 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1549 clock-names = "ipg", "ahb", "ptp",
1551 assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>,
1555 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
1559 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1560 fsl,num-tx-queues = <3>;
1561 fsl,num-rx-queues = <3>;
1562 nvmem-cells = <&fec_mac_address>;
1563 nvmem-cell-names = "mac-address";
1564 fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
1570 compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc";
1574 #interconnect-cells = <1>;
1575 operating-points-v2 = <&noc_opp_table>;
1577 noc_opp_table: opp-table {
1578 compatible = "operating-points-v2";
1580 opp-133000000 {
1581 opp-hz = /bits/ 64 <133333333>;
1584 opp-400000000 {
1585 opp-hz = /bits/ 64 <400000000>;
1588 opp-800000000 {
1589 opp-hz = /bits/ 64 <800000000>;
1595 compatible = "fsl,aips-bus", "simple-bus";
1597 #address-cells = <1>;
1598 #size-cells = <1>;
1601 irqsteer: interrupt-controller@32e2d000 {
1602 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
1606 clock-names = "ipg";
1608 fsl,num-irqs = <64>;
1609 interrupt-controller;
1610 #interrupt-cells = <1>;
1622 clock-names = "core", "shader", "bus", "reg";
1623 #cooling-cells = <2>;
1624 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>,
1629 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>,
1634 assigned-clock-rates = <800000000>, <800000000>,
1636 power-domains = <&pgc_gpu>;
1640 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1645 clock-names = "bus_early", "ref", "suspend";
1646 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1648 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1650 assigned-clock-rates = <500000000>, <100000000>;
1653 phy-names = "usb2-phy", "usb3-phy";
1654 power-domains = <&pgc_otg1>;
1655 snps,parkmode-disable-ss-quirk;
1659 usb3_phy0: usb-phy@381f0040 {
1660 compatible = "fsl,imx8mq-usb-phy";
1663 clock-names = "phy";
1664 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1665 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1666 assigned-clock-rates = <100000000>;
1667 #phy-cells = <0>;
1672 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
1677 clock-names = "bus_early", "ref", "suspend";
1678 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>,
1680 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>,
1682 assigned-clock-rates = <500000000>, <100000000>;
1685 phy-names = "usb2-phy", "usb3-phy";
1686 power-domains = <&pgc_otg2>;
1687 snps,parkmode-disable-ss-quirk;
1691 usb3_phy1: usb-phy@382f0040 {
1692 compatible = "fsl,imx8mq-usb-phy";
1695 clock-names = "phy";
1696 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>;
1697 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>;
1698 assigned-clock-rates = <100000000>;
1699 #phy-cells = <0>;
1703 vpu_g1: video-codec@38300000 {
1704 compatible = "nxp,imx8mq-vpu-g1";
1708 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>;
1711 vpu_g2: video-codec@38310000 {
1712 compatible = "nxp,imx8mq-vpu-g2";
1716 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>;
1719 vpu_blk_ctrl: blk-ctrl@38320000 {
1720 compatible = "fsl,imx8mq-vpu-blk-ctrl";
1722 power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>;
1723 power-domain-names = "bus", "g1", "g2";
1726 clock-names = "g1", "g2";
1727 #power-domain-cells = <1>;
1731 compatible = "fsl,imx8mq-pcie";
1734 reg-names = "dbi", "config";
1735 #address-cells = <3>;
1736 #size-cells = <2>;
1738 bus-range = <0x00 0xff>;
1740 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1741 num-lanes = <1>;
1743 interrupt-names = "msi";
1744 #interrupt-cells = <1>;
1745 interrupt-map-mask = <0 0 0 0x7>;
1746 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1750 fsl,max-link-speed = <2>;
1751 linux,pci-domain = <0>;
1756 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1757 power-domains = <&pgc_pcie>;
1761 reset-names = "pciephy", "apps", "turnoff";
1762 assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>,
1765 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1768 assigned-clock-rates = <250000000>, <100000000>,
1773 pcie0_ep: pcie-ep@33800000 {
1774 compatible = "fsl,imx8mq-pcie-ep";
1779 reg-names = "dbi", "addr_space", "dbi2", "atu";
1780 num-lanes = <1>;
1782 interrupt-names = "dma";
1783 linux,pci-domain = <0>;
1788 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1789 power-domains = <&pgc_pcie>;
1793 reset-names = "pciephy", "apps", "turnoff";
1794 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
1797 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1800 assigned-clock-rates = <250000000>, <100000000>,
1802 num-ib-windows = <4>;
1803 num-ob-windows = <4>;
1804 fsl,max-link-speed = <2>;
1809 compatible = "fsl,imx8mq-pcie";
1812 reg-names = "dbi", "config";
1813 #address-cells = <3>;
1814 #size-cells = <2>;
1816 bus-range = <0x00 0xff>;
1818 <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1819 num-lanes = <1>;
1821 interrupt-names = "msi";
1822 #interrupt-cells = <1>;
1823 interrupt-map-mask = <0 0 0 0x7>;
1824 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1828 fsl,max-link-speed = <2>;
1829 linux,pci-domain = <1>;
1834 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1835 power-domains = <&pgc_pcie>;
1839 reset-names = "pciephy", "apps", "turnoff";
1840 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
1843 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1846 assigned-clock-rates = <250000000>, <100000000>,
1851 pcie1_ep: pcie-ep@33c00000 {
1852 compatible = "fsl,imx8mq-pcie-ep";
1857 reg-names = "dbi", "addr_space", "dbi2", "atu";
1858 num-lanes = <1>;
1860 interrupt-names = "dma";
1861 fsl,max-link-speed = <2>;
1862 linux,pci-domain = <1>;
1867 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
1868 power-domains = <&pgc_pcie>;
1872 reset-names = "pciephy", "apps", "turnoff";
1873 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
1876 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
1879 assigned-clock-rates = <250000000>, <100000000>,
1881 num-ib-windows = <4>;
1882 num-ob-windows = <4>;
1886 gic: interrupt-controller@38800000 {
1887 compatible = "arm,gic-v3";
1893 #interrupt-cells = <3>;
1894 interrupt-controller;
1896 interrupt-parent = <&gic>;
1899 ddrc: memory-controller@3d400000 {
1900 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc";
1902 clock-names = "core", "pll", "alt", "apb";
1910 ddr-pmu@3d800000 {
1911 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu";
1913 interrupt-parent = <&gic>;