Lines Matching +full:0 +full:x31020000
47 #clock-cells = <0>;
54 #clock-cells = <0>;
61 #clock-cells = <0>;
68 #clock-cells = <0>;
75 #clock-cells = <0>;
82 #clock-cells = <0>;
89 #clock-cells = <0>;
96 #clock-cells = <0>;
103 #size-cells = <0>;
105 A53_0: cpu@0 {
108 reg = <0x0>;
111 i-cache-size = <0x8000>;
114 d-cache-size = <0x8000>;
127 reg = <0x1>;
130 i-cache-size = <0x8000>;
133 d-cache-size = <0x8000>;
144 reg = <0x2>;
147 i-cache-size = <0x8000>;
150 d-cache-size = <0x8000>;
161 reg = <0x3>;
164 i-cache-size = <0x8000>;
167 d-cache-size = <0x8000>;
179 cache-size = <0x100000>;
193 opp-supported-hw = <0xf>, <0x4>;
202 opp-supported-hw = <0xe>, <0x3>;
210 opp-supported-hw = <0xc>, <0x4>;
218 opp-supported-hw = <0x8>, <0x3>;
233 #size-cells = <0>;
235 port@0 {
236 reg = <0>;
292 thermal-sensors = <&tmu 0>;
373 soc: soc@0 {
377 ranges = <0x0 0x0 0x0 0x3e000000>;
378 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
384 reg = <0x28440000 0x1000>;
400 reg = <0x28540000 0x1000>;
416 reg = <0x28640000 0x1000>;
432 reg = <0x28740000 0x1000>;
448 reg = <0x28c03000 0x1000>;
454 #size-cells = <0>;
456 port@0 {
457 reg = <0>;
485 reg = <0x28c04000 0x1000>;
508 reg = <0x28c06000 0x1000>;
523 reg = <0x30000000 0x400000>;
526 ranges = <0x30000000 0x30000000 0x400000>;
529 #sound-dai-cells = <0>;
531 reg = <0x30010000 0x10000>;
537 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>;
543 #sound-dai-cells = <0>;
545 reg = <0x30030000 0x10000>;
551 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>;
557 #sound-dai-cells = <0>;
559 reg = <0x30040000 0x10000>;
565 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>;
571 #sound-dai-cells = <0>;
573 reg = <0x30050000 0x10000>;
579 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>;
586 reg = <0x30200000 0x10000>;
594 gpio-ranges = <&iomuxc 0 10 30>;
599 reg = <0x30210000 0x10000>;
607 gpio-ranges = <&iomuxc 0 40 21>;
612 reg = <0x30220000 0x10000>;
620 gpio-ranges = <&iomuxc 0 61 26>;
625 reg = <0x30230000 0x10000>;
633 gpio-ranges = <&iomuxc 0 87 32>;
638 reg = <0x30240000 0x10000>;
646 gpio-ranges = <&iomuxc 0 119 30>;
651 reg = <0x30260000 0x10000>;
655 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>;
656 fsl,tmu-calibration = <0x00000000 0x00000023>,
657 <0x00000001 0x00000029>,
658 <0x00000002 0x0000002f>,
659 <0x00000003 0x00000035>,
660 <0x00000004 0x0000003d>,
661 <0x00000005 0x00000043>,
662 <0x00000006 0x0000004b>,
663 <0x00000007 0x00000051>,
664 <0x00000008 0x00000057>,
665 <0x00000009 0x0000005f>,
666 <0x0000000a 0x00000067>,
667 <0x0000000b 0x0000006f>,
669 <0x00010000 0x0000001b>,
670 <0x00010001 0x00000023>,
671 <0x00010002 0x0000002b>,
672 <0x00010003 0x00000033>,
673 <0x00010004 0x0000003b>,
674 <0x00010005 0x00000043>,
675 <0x00010006 0x0000004b>,
676 <0x00010007 0x00000055>,
677 <0x00010008 0x0000005d>,
678 <0x00010009 0x00000067>,
679 <0x0001000a 0x00000070>,
681 <0x00020000 0x00000017>,
682 <0x00020001 0x00000023>,
683 <0x00020002 0x0000002d>,
684 <0x00020003 0x00000037>,
685 <0x00020004 0x00000041>,
686 <0x00020005 0x0000004b>,
687 <0x00020006 0x00000057>,
688 <0x00020007 0x00000063>,
689 <0x00020008 0x0000006f>,
691 <0x00030000 0x00000015>,
692 <0x00030001 0x00000021>,
693 <0x00030002 0x0000002d>,
694 <0x00030003 0x00000039>,
695 <0x00030004 0x00000045>,
696 <0x00030005 0x00000053>,
697 <0x00030006 0x0000005f>,
698 <0x00030007 0x00000071>;
704 reg = <0x30280000 0x10000>;
712 reg = <0x30290000 0x10000>;
720 reg = <0x302a0000 0x10000>;
728 reg = <0x302c0000 0x10000>;
739 reg = <0x30320000 0x10000>;
752 assigned-clock-rates = <0>, <0>, <0>, <594000000>;
764 reg = <0x30330000 0x10000>;
769 reg = <0x30340000 0x10000>;
774 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */
780 reg = <0x30350000 0x10000>;
791 * Fuse Address = (ADDR * 4) + 0x400
794 * +0x10 in Fusemap Description Table (e.g.
795 * reg = <0x4 0x8> describes fuses 0x410 and
796 * 0x420).
798 imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */
799 reg = <0x4 0x8>;
802 cpu_speed_grade: speed-grade@10 { /* 0x440 */
803 reg = <0x10 4>;
806 fec_mac_address: mac-address@90 { /* 0x640 */
807 reg = <0x90 6>;
813 reg = <0x30360000 0x10000>;
819 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
820 reg = <0x30370000 0x10000>;
823 compatible = "fsl,sec-v4.0-mon-rtc-lp";
825 offset = <0x34>;
833 compatible = "fsl,sec-v4.0-pwrkey";
846 reg = <0x30380000 0x10000>;
864 assigned-clock-rates = <0>, <0>,
866 <0>,
867 <0>,
868 <0>,
873 <0>,
881 reg = <0x30390000 0x10000>;
888 reg = <0x303a0000 0x10000>;
896 #size-cells = <0>;
898 pgc_mipi: power-domain@0 {
899 #power-domain-cells = <0>;
919 #power-domain-cells = <0>;
925 #power-domain-cells = <0>;
930 #power-domain-cells = <0>;
935 #power-domain-cells = <0>;
940 #power-domain-cells = <0>;
949 #power-domain-cells = <0>;
965 <0>;
969 #power-domain-cells = <0>;
974 #power-domain-cells = <0>;
979 #power-domain-cells = <0>;
984 #power-domain-cells = <0>;
993 reg = <0x30400000 0x400000>;
996 ranges = <0x30400000 0x30400000 0x400000>;
1000 reg = <0x30660000 0x10000>;
1011 reg = <0x30670000 0x10000>;
1022 reg = <0x30680000 0x10000>;
1033 reg = <0x30690000 0x10000>;
1044 reg = <0x306a0000 0x20000>;
1053 reg = <0x30800000 0x400000>;
1056 ranges = <0x30800000 0x30800000 0x400000>,
1057 <0x08000000 0x08000000 0x10000000>;
1061 reg = <0x30810000 0x10000>;
1078 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>;
1085 #size-cells = <0>;
1087 reg = <0x30820000 0x10000>;
1092 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1099 #size-cells = <0>;
1101 reg = <0x30830000 0x10000>;
1113 #size-cells = <0>;
1115 reg = <0x30840000 0x10000>;
1128 reg = <0x30860000 0x10000>;
1133 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
1141 reg = <0x30880000 0x10000>;
1146 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
1154 reg = <0x30890000 0x10000>;
1159 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
1166 reg = <0x308a0000 0x10000>;
1183 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>;
1189 #sound-dai-cells = <0>;
1191 reg = <0x308b0000 0x10000>;
1197 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>;
1203 #sound-dai-cells = <0>;
1205 reg = <0x308c0000 0x10000>;
1211 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>;
1217 compatible = "fsl,sec-v4.0";
1220 reg = <0x30900000 0x40000>;
1221 ranges = <0 0x30900000 0x40000>;
1228 compatible = "fsl,sec-v4.0-job-ring";
1229 reg = <0x1000 0x1000>;
1235 compatible = "fsl,sec-v4.0-job-ring";
1236 reg = <0x2000 0x1000>;
1241 compatible = "fsl,sec-v4.0-job-ring";
1242 reg = <0x3000 0x1000>;
1249 reg = <0x30a00000 0x300>;
1251 #size-cells = <0>;
1265 mux-controls = <&mux 0>;
1278 #size-cells = <0>;
1280 port@0 {
1281 reg = <0>;
1283 #size-cells = <0>;
1284 mipi_dsi_lcdif_in: endpoint@0 {
1285 reg = <0>;
1301 reg = <0x30a00300 0x100>;
1311 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>;
1312 #phy-cells = <0>;
1319 reg = <0x30a20000 0x10000>;
1323 #size-cells = <0>;
1329 reg = <0x30a30000 0x10000>;
1333 #size-cells = <0>;
1339 reg = <0x30a40000 0x10000>;
1343 #size-cells = <0>;
1349 reg = <0x30a50000 0x10000>;
1353 #size-cells = <0>;
1360 reg = <0x30a60000 0x10000>;
1365 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1372 reg = <0x30a70000 0x1000>;
1388 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
1395 #size-cells = <0>;
1409 reg = <0x30a90000 0x10000>;
1424 reg = <0x30b60000 0x1000>;
1440 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>;
1447 #size-cells = <0>;
1461 reg = <0x30b80000 0x10000>;
1476 reg = <0x30aa0000 0x10000>;
1485 reg = <0x30b40000 0x10000>;
1500 reg = <0x30b50000 0x10000>;
1514 #size-cells = <0>;
1516 reg = <0x30bb0000 0x10000>,
1517 <0x08000000 0x10000000>;
1528 reg = <0x30bd0000 0x10000>;
1539 reg = <0x30be0000 0x10000>;
1559 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1564 fsl,stop-mode = <&iomuxc_gpr 0x10 3>;
1571 reg = <0x32700000 0x100000>;
1596 reg = <0x32c00000 0x400000>;
1599 ranges = <0x32c00000 0x32c00000 0x400000>;
1603 reg = <0x32e2d000 0x1000>;
1607 fsl,channel = <0>;
1616 reg = <0x38000000 0x40000>;
1635 <800000000>, <800000000>, <0>;
1641 reg = <0x38100000 0x10000>;
1661 reg = <0x381f0040 0x40>;
1667 #phy-cells = <0>;
1673 reg = <0x38200000 0x10000>;
1693 reg = <0x382f0040 0x40>;
1699 #phy-cells = <0>;
1705 reg = <0x38300000 0x10000>;
1713 reg = <0x38310000 0x10000>;
1721 reg = <0x38320000 0x100>;
1732 reg = <0x33800000 0x400000>,
1733 <0x1ff00000 0x80000>;
1738 bus-range = <0x00 0xff>;
1739 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
1740 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1745 interrupt-map-mask = <0 0 0 0x7>;
1746 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1747 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1748 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1749 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1751 linux,pci-domain = <0>;
1775 reg = <0x33800000 0x100000>,
1776 <0x18000000 0x8000000>,
1777 <0x33900000 0x100000>,
1778 <0x33b00000 0x100000>;
1783 linux,pci-domain = <0>;
1810 reg = <0x33c00000 0x400000>,
1811 <0x27f00000 0x80000>;
1816 bus-range = <0x00 0xff>;
1817 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */
1818 <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */
1823 interrupt-map-mask = <0 0 0 0x7>;
1824 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
1825 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
1826 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1827 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1853 reg = <0x33c00000 0x100000>,
1854 <0x20000000 0x8000000>,
1855 <0x33d00000 0x100000>,
1856 <0x33f00000 0x100000>;
1888 reg = <0x38800000 0x10000>, /* GIC Dist */
1889 <0x38880000 0xc0000>, /* GICR */
1890 <0x31000000 0x2000>, /* GICC */
1891 <0x31010000 0x2000>, /* GICV */
1892 <0x31020000 0x2000>; /* GICH */
1901 reg = <0x3d400000 0x400000>;
1912 reg = <0x3d800000 0x400000>;