Lines Matching +full:sysctr +full:- +full:timer
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/reset/imx8mp-reset-audiomix.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interconnect/fsl,imx8mp.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/thermal/thermal.h>
16 #include "imx8mp-pinfunc.h"
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
48 #address-cells = <1>;
49 #size-cells = <0>;
51 idle-states {
52 entry-method = "psci";
54 cpu_pd_wait: cpu-pd-wait {
55 compatible = "arm,idle-state";
56 arm,psci-suspend-param = <0x0010033>;
57 local-timer-stop;
58 entry-latency-us = <1000>;
59 exit-latency-us = <700>;
60 min-residency-us = <2700>;
61 wakeup-latency-us = <1500>;
67 compatible = "arm,cortex-a53";
70 enable-method = "psci";
71 i-cache-size = <0x8000>;
72 i-cache-line-size = <64>;
73 i-cache-sets = <256>;
74 d-cache-size = <0x8000>;
75 d-cache-line-size = <64>;
76 d-cache-sets = <128>;
77 next-level-cache = <&A53_L2>;
78 nvmem-cells = <&cpu_speed_grade>;
79 nvmem-cell-names = "speed_grade";
80 operating-points-v2 = <&a53_opp_table>;
81 #cooling-cells = <2>;
82 cpu-idle-states = <&cpu_pd_wait>;
87 compatible = "arm,cortex-a53";
90 enable-method = "psci";
91 i-cache-size = <0x8000>;
92 i-cache-line-size = <64>;
93 i-cache-sets = <256>;
94 d-cache-size = <0x8000>;
95 d-cache-line-size = <64>;
96 d-cache-sets = <128>;
97 next-level-cache = <&A53_L2>;
98 operating-points-v2 = <&a53_opp_table>;
99 #cooling-cells = <2>;
100 cpu-idle-states = <&cpu_pd_wait>;
105 compatible = "arm,cortex-a53";
108 enable-method = "psci";
109 i-cache-size = <0x8000>;
110 i-cache-line-size = <64>;
111 i-cache-sets = <256>;
112 d-cache-size = <0x8000>;
113 d-cache-line-size = <64>;
114 d-cache-sets = <128>;
115 next-level-cache = <&A53_L2>;
116 operating-points-v2 = <&a53_opp_table>;
117 #cooling-cells = <2>;
118 cpu-idle-states = <&cpu_pd_wait>;
123 compatible = "arm,cortex-a53";
126 enable-method = "psci";
127 i-cache-size = <0x8000>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
133 next-level-cache = <&A53_L2>;
134 operating-points-v2 = <&a53_opp_table>;
135 #cooling-cells = <2>;
136 cpu-idle-states = <&cpu_pd_wait>;
139 A53_L2: l2-cache0 {
141 cache-unified;
142 cache-level = <2>;
143 cache-size = <0x80000>;
144 cache-line-size = <64>;
145 cache-sets = <512>;
149 a53_opp_table: opp-table {
150 compatible = "operating-points-v2";
151 opp-shared;
153 opp-1200000000 {
154 opp-hz = /bits/ 64 <1200000000>;
155 opp-microvolt = <850000>;
156 opp-supported-hw = <0x8a0>, <0x7>;
157 clock-latency-ns = <150000>;
158 opp-suspend;
161 opp-1600000000 {
162 opp-hz = /bits/ 64 <1600000000>;
163 opp-microvolt = <950000>;
164 opp-supported-hw = <0xa0>, <0x7>;
165 clock-latency-ns = <150000>;
166 opp-suspend;
169 opp-1800000000 {
170 opp-hz = /bits/ 64 <1800000000>;
171 opp-microvolt = <1000000>;
172 opp-supported-hw = <0x20>, <0x3>;
173 clock-latency-ns = <150000>;
174 opp-suspend;
178 osc_32k: clock-osc-32k {
179 compatible = "fixed-clock";
180 #clock-cells = <0>;
181 clock-frequency = <32768>;
182 clock-output-names = "osc_32k";
185 osc_24m: clock-osc-24m {
186 compatible = "fixed-clock";
187 #clock-cells = <0>;
188 clock-frequency = <24000000>;
189 clock-output-names = "osc_24m";
192 clk_ext1: clock-ext1 {
193 compatible = "fixed-clock";
194 #clock-cells = <0>;
195 clock-frequency = <133000000>;
196 clock-output-names = "clk_ext1";
199 clk_ext2: clock-ext2 {
200 compatible = "fixed-clock";
201 #clock-cells = <0>;
202 clock-frequency = <133000000>;
203 clock-output-names = "clk_ext2";
206 clk_ext3: clock-ext3 {
207 compatible = "fixed-clock";
208 #clock-cells = <0>;
209 clock-frequency = <133000000>;
210 clock-output-names = "clk_ext3";
213 clk_ext4: clock-ext4 {
214 compatible = "fixed-clock";
215 #clock-cells = <0>;
216 clock-frequency = <133000000>;
217 clock-output-names = "clk_ext4";
222 * non-configurable funnel don't show up on the AMBA
225 compatible = "arm,coresight-static-funnel";
227 in-ports {
228 #address-cells = <1>;
229 #size-cells = <0>;
235 remote-endpoint = <&etm0_out_port>;
243 remote-endpoint = <&etm1_out_port>;
251 remote-endpoint = <&etm2_out_port>;
259 remote-endpoint = <&etm3_out_port>;
264 out-ports {
268 remote-endpoint = <&hugo_funnel_in_port0>;
274 reserved-memory {
275 #address-cells = <2>;
276 #size-cells = <2>;
281 no-map;
287 compatible = "arm,cortex-a53-pmu";
293 compatible = "arm,psci-1.0";
297 thermal-zones {
298 cpu-thermal {
299 polling-delay-passive = <250>;
300 polling-delay = <2000>;
301 thermal-sensors = <&tmu 0>;
316 cooling-maps {
319 cooling-device =
331 soc-thermal {
332 polling-delay-passive = <250>;
333 polling-delay = <2000>;
334 thermal-sensors = <&tmu 1>;
349 cooling-maps {
352 cooling-device =
365 timer {
366 compatible = "arm,armv8-timer";
371 clock-frequency = <8000000>;
372 arm,no-tick-in-suspend;
376 compatible = "fsl,imx8mp-soc", "simple-bus";
377 #address-cells = <1>;
378 #size-cells = <1>;
380 nvmem-cells = <&imx8mp_uid>;
381 nvmem-cell-names = "soc_unique_id";
384 compatible = "arm,coresight-etm4x", "arm,primecell";
388 clock-names = "apb_pclk";
390 out-ports {
393 remote-endpoint = <&ca_funnel_in_port0>;
400 compatible = "arm,coresight-etm4x", "arm,primecell";
404 clock-names = "apb_pclk";
406 out-ports {
409 remote-endpoint = <&ca_funnel_in_port1>;
416 compatible = "arm,coresight-etm4x", "arm,primecell";
420 clock-names = "apb_pclk";
422 out-ports {
425 remote-endpoint = <&ca_funnel_in_port2>;
432 compatible = "arm,coresight-etm4x", "arm,primecell";
436 clock-names = "apb_pclk";
438 out-ports {
441 remote-endpoint = <&ca_funnel_in_port3>;
448 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
451 clock-names = "apb_pclk";
453 in-ports {
454 #address-cells = <1>;
455 #size-cells = <0>;
461 remote-endpoint = <&ca_funnel_out_port0>;
483 out-ports {
486 remote-endpoint = <&etf_in_port>;
493 compatible = "arm,coresight-tmc", "arm,primecell";
496 clock-names = "apb_pclk";
498 in-ports {
501 remote-endpoint = <&hugo_funnel_out_port0>;
506 out-ports {
509 remote-endpoint = <&etr_in_port>;
516 compatible = "arm,coresight-tmc", "arm,primecell";
519 clock-names = "apb_pclk";
521 in-ports {
524 remote-endpoint = <&etf_out_port>;
531 compatible = "fsl,aips-bus", "simple-bus";
533 #address-cells = <1>;
534 #size-cells = <1>;
538 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
543 gpio-controller;
544 #gpio-cells = <2>;
545 interrupt-controller;
546 #interrupt-cells = <2>;
547 gpio-ranges = <&iomuxc 0 5 30>;
551 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
556 gpio-controller;
557 #gpio-cells = <2>;
558 interrupt-controller;
559 #interrupt-cells = <2>;
560 gpio-ranges = <&iomuxc 0 35 21>;
564 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
569 gpio-controller;
570 #gpio-cells = <2>;
571 interrupt-controller;
572 #interrupt-cells = <2>;
573 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
577 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
582 gpio-controller;
583 #gpio-cells = <2>;
584 interrupt-controller;
585 #interrupt-cells = <2>;
586 gpio-ranges = <&iomuxc 0 82 32>;
590 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
595 gpio-controller;
596 #gpio-cells = <2>;
597 interrupt-controller;
598 #interrupt-cells = <2>;
599 gpio-ranges = <&iomuxc 0 114 30>;
603 compatible = "fsl,imx8mp-tmu";
606 nvmem-cells = <&tmu_calib>;
607 nvmem-cell-names = "calib";
608 #thermal-sensor-cells = <1>;
612 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
620 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
628 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
635 gpt1: timer@302d0000 {
636 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
640 clock-names = "ipg", "per";
643 gpt2: timer@302e0000 {
644 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
648 clock-names = "ipg", "per";
651 gpt3: timer@302f0000 {
652 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
656 clock-names = "ipg", "per";
660 compatible = "fsl,imx8mp-iomuxc";
665 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
670 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
674 #address-cells = <1>;
675 #size-cells = <1>;
690 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
694 cpu_speed_grade: speed-grade@10 { /* 0x440 */
698 eth_mac1: mac-address@90 { /* 0x640 */
702 eth_mac2: mac-address@96 { /* 0x658 */
706 tmu_calib: calib@264 { /* 0xd90-0xdc0 */
711 anatop: clock-controller@30360000 {
712 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
714 #clock-cells = <1>;
718 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
721 snvs_rtc: snvs-rtc-lp {
722 compatible = "fsl,sec-v4.0-mon-rtc-lp";
728 clock-names = "snvs-rtc";
731 snvs_pwrkey: snvs-powerkey {
732 compatible = "fsl,sec-v4.0-pwrkey";
736 clock-names = "snvs-pwrkey";
738 wakeup-source;
742 snvs_lpgpr: snvs-lpgpr {
743 compatible = "fsl,imx8mp-snvs-lpgpr",
744 "fsl,imx7d-snvs-lpgpr";
748 clk: clock-controller@30380000 {
749 compatible = "fsl,imx8mp-ccm";
753 #clock-cells = <1>;
756 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
758 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
763 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
768 assigned-clock-rates = <0>, <0>,
774 src: reset-controller@30390000 {
775 compatible = "fsl,imx8mp-src", "syscon";
778 #reset-cells = <1>;
782 compatible = "fsl,imx8mp-gpc";
784 interrupt-parent = <&gic>;
786 interrupt-controller;
787 #interrupt-cells = <3>;
790 #address-cells = <1>;
791 #size-cells = <0>;
793 pgc_mipi_phy1: power-domain@0 {
794 #power-domain-cells = <0>;
798 pgc_pcie_phy: power-domain@1 {
799 #power-domain-cells = <0>;
803 pgc_usb1_phy: power-domain@2 {
804 #power-domain-cells = <0>;
808 pgc_usb2_phy: power-domain@3 {
809 #power-domain-cells = <0>;
813 pgc_mlmix: power-domain@4 {
814 #power-domain-cells = <0>;
819 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
822 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
825 assigned-clock-rates = <1000000000>,
830 pgc_audio: power-domain@5 {
831 #power-domain-cells = <0>;
835 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
837 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
839 assigned-clock-rates = <400000000>,
843 pgc_gpu2d: power-domain@6 {
844 #power-domain-cells = <0>;
847 power-domains = <&pgc_gpumix>;
850 pgc_gpumix: power-domain@7 {
851 #power-domain-cells = <0>;
855 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
857 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
859 assigned-clock-rates = <800000000>, <400000000>;
862 pgc_vpumix: power-domain@8 {
863 #power-domain-cells = <0>;
868 pgc_gpu3d: power-domain@9 {
869 #power-domain-cells = <0>;
873 power-domains = <&pgc_gpumix>;
876 pgc_mediamix: power-domain@10 {
877 #power-domain-cells = <0>;
883 pgc_vpu_g1: power-domain@11 {
884 #power-domain-cells = <0>;
888 pgc_vpu_g2: power-domain@12 {
889 #power-domain-cells = <0>;
893 pgc_vpu_vc8000e: power-domain@13 {
894 #power-domain-cells = <0>;
898 pgc_hdmimix: power-domain@14 {
899 #power-domain-cells = <0>;
903 assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
905 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
907 assigned-clock-rates = <500000000>, <133000000>;
910 pgc_hdmi_phy: power-domain@15 {
911 #power-domain-cells = <0>;
915 pgc_mipi_phy2: power-domain@16 {
916 #power-domain-cells = <0>;
920 pgc_hsiomix: power-domain@17 {
921 #power-domain-cells = <0>;
925 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
926 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
927 assigned-clock-rates = <500000000>;
930 pgc_ispdwp: power-domain@18 {
931 #power-domain-cells = <0>;
940 compatible = "fsl,aips-bus", "simple-bus";
942 #address-cells = <1>;
943 #size-cells = <1>;
947 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
952 clock-names = "ipg", "per";
953 #pwm-cells = <3>;
958 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
963 clock-names = "ipg", "per";
964 #pwm-cells = <3>;
969 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
974 clock-names = "ipg", "per";
975 #pwm-cells = <3>;
980 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
985 clock-names = "ipg", "per";
986 #pwm-cells = <3>;
990 system_counter: timer@306a0000 {
991 compatible = "nxp,sysctr-timer";
995 clock-names = "per";
998 gpt6: timer@306e0000 {
999 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
1003 clock-names = "ipg", "per";
1006 gpt5: timer@306f0000 {
1007 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
1011 clock-names = "ipg", "per";
1014 gpt4: timer@30700000 {
1015 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
1019 clock-names = "ipg", "per";
1024 compatible = "fsl,aips-bus", "simple-bus";
1026 #address-cells = <1>;
1027 #size-cells = <1>;
1030 spba-bus@30800000 {
1031 compatible = "fsl,spba-bus", "simple-bus";
1033 #address-cells = <1>;
1034 #size-cells = <1>;
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1040 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1045 clock-names = "ipg", "per";
1046 assigned-clock-rates = <80000000>;
1047 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
1048 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1050 dma-names = "rx", "tx";
1055 #address-cells = <1>;
1056 #size-cells = <0>;
1057 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1062 clock-names = "ipg", "per";
1063 assigned-clock-rates = <80000000>;
1064 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
1065 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1067 dma-names = "rx", "tx";
1072 #address-cells = <1>;
1073 #size-cells = <0>;
1074 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1079 clock-names = "ipg", "per";
1080 assigned-clock-rates = <80000000>;
1081 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
1082 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1084 dma-names = "rx", "tx";
1089 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1094 clock-names = "ipg", "per";
1096 dma-names = "rx", "tx";
1101 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1106 clock-names = "ipg", "per";
1108 dma-names = "rx", "tx";
1113 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1118 clock-names = "ipg", "per";
1120 dma-names = "rx", "tx";
1125 compatible = "fsl,imx8mp-flexcan";
1130 clock-names = "ipg", "per";
1131 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
1132 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1133 assigned-clock-rates = <40000000>;
1134 fsl,clk-source = /bits/ 8 <0>;
1135 fsl,stop-mode = <&gpr 0x10 4>;
1140 compatible = "fsl,imx8mp-flexcan";
1145 clock-names = "ipg", "per";
1146 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
1147 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1148 assigned-clock-rates = <40000000>;
1149 fsl,clk-source = /bits/ 8 <0>;
1150 fsl,stop-mode = <&gpr 0x10 5>;
1156 compatible = "fsl,sec-v4.0";
1157 #address-cells = <1>;
1158 #size-cells = <1>;
1164 clock-names = "aclk", "ipg";
1167 compatible = "fsl,sec-v4.0-job-ring";
1174 compatible = "fsl,sec-v4.0-job-ring";
1180 compatible = "fsl,sec-v4.0-job-ring";
1187 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1188 #address-cells = <1>;
1189 #size-cells = <0>;
1197 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1198 #address-cells = <1>;
1199 #size-cells = <0>;
1207 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1208 #address-cells = <1>;
1209 #size-cells = <0>;
1217 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1218 #address-cells = <1>;
1219 #size-cells = <0>;
1227 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1232 clock-names = "ipg", "per";
1234 dma-names = "rx", "tx";
1239 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1243 #mbox-cells = <2>;
1247 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1250 #mbox-cells = <2>;
1256 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1257 #address-cells = <1>;
1258 #size-cells = <0>;
1266 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1267 #address-cells = <1>;
1268 #size-cells = <0>;
1276 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1282 clock-names = "ipg", "ahb", "per";
1283 fsl,tuning-start-tap = <20>;
1284 fsl,tuning-step = <2>;
1285 bus-width = <4>;
1290 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1296 clock-names = "ipg", "ahb", "per";
1297 fsl,tuning-start-tap = <20>;
1298 fsl,tuning-step = <2>;
1299 bus-width = <4>;
1304 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1310 clock-names = "ipg", "ahb", "per";
1311 fsl,tuning-start-tap = <20>;
1312 fsl,tuning-step = <2>;
1313 bus-width = <4>;
1318 compatible = "nxp,imx8mp-fspi";
1320 reg-names = "fspi_base", "fspi_mmap";
1324 clock-names = "fspi_en", "fspi";
1325 assigned-clock-rates = <80000000>;
1326 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
1327 #address-cells = <1>;
1328 #size-cells = <0>;
1332 sdma1: dma-controller@30bd0000 {
1333 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1338 clock-names = "ipg", "ahb";
1339 #dma-cells = <3>;
1340 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1344 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1355 clock-names = "ipg", "ahb", "ptp",
1357 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1361 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1365 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1366 fsl,num-tx-queues = <3>;
1367 fsl,num-rx-queues = <3>;
1368 nvmem-cells = <ð_mac1>;
1369 nvmem-cell-names = "mac-address";
1370 fsl,stop-mode = <&gpr 0x10 3>;
1375 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1379 interrupt-names = "macirq", "eth_wake_irq";
1384 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1385 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1388 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1391 assigned-clock-rates = <0>, <100000000>, <125000000>;
1392 nvmem-cells = <ð_mac2>;
1393 nvmem-cell-names = "mac-address";
1400 compatible = "fsl,aips-bus", "simple-bus";
1402 #address-cells = <1>;
1403 #size-cells = <1>;
1406 spba-bus@30c00000 {
1407 compatible = "fsl,spba-bus", "simple-bus";
1409 #address-cells = <1>;
1410 #size-cells = <1>;
1414 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1416 #sound-dai-cells = <0>;
1422 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1424 dma-names = "rx", "tx";
1430 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1432 #sound-dai-cells = <0>;
1438 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1440 dma-names = "rx", "tx";
1446 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1448 #sound-dai-cells = <0>;
1454 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1456 dma-names = "rx", "tx";
1462 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1464 #sound-dai-cells = <0>;
1470 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1472 dma-names = "rx", "tx";
1478 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1480 #sound-dai-cells = <0>;
1486 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1488 dma-names = "rx", "tx";
1494 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1496 #sound-dai-cells = <0>;
1502 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1504 dma-names = "rx", "tx";
1510 compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc";
1514 clock-names = "mem";
1519 dma-names = "ctx0_rx", "ctx0_tx",
1523 firmware-name = "imx/easrc/easrc-imx8mn.bin";
1524 fsl,asrc-rate = <8000>;
1525 fsl,asrc-format = <2>;
1529 micfil: audio-controller@30ca0000 {
1530 compatible = "fsl,imx8mp-micfil";
1532 #sound-dai-cells = <0>;
1542 clock-names = "ipg_clk", "ipg_clk_app",
1545 dma-names = "rx";
1550 compatible = "fsl,imx8mp-aud2htx";
1554 clock-names = "bus";
1556 dma-names = "tx";
1561 compatible = "fsl,imx8mp-xcvr";
1566 reg-names = "ram", "regs", "rxfifo",
1572 /* XCVR PHY - SPDIF wakeup IRQ */
1578 clock-names = "ipg", "phy", "spba", "pll_ipg";
1580 dma-names = "rx", "tx";
1586 sdma3: dma-controller@30e00000 {
1587 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1589 #dma-cells = <3>;
1592 clock-names = "ipg", "ahb";
1594 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1597 sdma2: dma-controller@30e10000 {
1598 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1600 #dma-cells = <3>;
1603 clock-names = "ipg", "ahb";
1605 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1608 audio_blk_ctrl: clock-controller@30e20000 {
1609 compatible = "fsl,imx8mp-audio-blk-ctrl";
1611 #clock-cells = <1>;
1612 #reset-cells = <1>;
1621 clock-names = "ahb",
1624 power-domains = <&pgc_audio>;
1625 assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>,
1627 assigned-clock-rates = <393216000>, <361267200>;
1632 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1635 #interconnect-cells = <1>;
1636 operating-points-v2 = <&noc_opp_table>;
1638 noc_opp_table: opp-table {
1639 compatible = "operating-points-v2";
1641 opp-200000000 {
1642 opp-hz = /bits/ 64 <200000000>;
1646 opp-800000000 {
1647 opp-hz = /bits/ 64 <800000000>;
1651 opp-1000000000 {
1652 opp-hz = /bits/ 64 <1000000000>;
1658 compatible = "fsl,aips-bus", "simple-bus";
1660 #address-cells = <1>;
1661 #size-cells = <1>;
1665 compatible = "fsl,imx8mp-isi";
1671 clock-names = "axi", "apb";
1672 fsl,blk-ctrl = <&media_blk_ctrl>;
1673 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
1677 #address-cells = <1>;
1678 #size-cells = <0>;
1684 remote-endpoint = <&mipi_csi_0_out>;
1692 remote-endpoint = <&mipi_csi_1_out>;
1699 compatible = "fsl,imx8mp-isp";
1705 clock-names = "isp", "aclk", "hclk";
1706 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
1707 fsl,blk-ctrl = <&media_blk_ctrl 0>;
1711 #address-cells = <1>;
1712 #size-cells = <0>;
1721 compatible = "fsl,imx8mp-isp";
1727 clock-names = "isp", "aclk", "hclk";
1728 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
1729 fsl,blk-ctrl = <&media_blk_ctrl 1>;
1733 #address-cells = <1>;
1734 #size-cells = <0>;
1743 compatible = "nxp,imx8mp-dw100";
1748 clock-names = "axi", "ahb";
1749 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
1753 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1756 clock-frequency = <250000000>;
1761 clock-names = "pclk", "wrap", "phy", "axi";
1762 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
1764 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
1766 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
1770 #address-cells = <1>;
1771 #size-cells = <0>;
1781 remote-endpoint = <&isi_in_0>;
1788 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1791 clock-frequency = <250000000>;
1796 clock-names = "pclk", "wrap", "phy", "axi";
1797 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
1799 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
1801 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
1805 #address-cells = <1>;
1806 #size-cells = <0>;
1816 remote-endpoint = <&isi_in_1>;
1823 compatible = "fsl,imx8mp-mipi-dsim";
1827 clock-names = "bus_clk", "sclk_mipi";
1828 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
1830 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1832 assigned-clock-rates = <200000000>, <24000000>;
1833 samsung,pll-clock-frequency = <24000000>;
1835 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
1839 #address-cells = <1>;
1840 #size-cells = <0>;
1846 remote-endpoint = <&lcdif1_to_dsim>;
1859 lcdif1: display-controller@32e80000 {
1860 compatible = "fsl,imx8mp-lcdif";
1865 clock-names = "pix", "axi", "disp_axi";
1867 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
1872 remote-endpoint = <&dsim_from_lcdif1>;
1877 lcdif2: display-controller@32e90000 {
1878 compatible = "fsl,imx8mp-lcdif";
1884 clock-names = "pix", "axi", "disp_axi";
1885 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;
1890 remote-endpoint = <&ldb_from_lcdif2>;
1895 media_blk_ctrl: blk-ctrl@32ec0000 {
1896 compatible = "fsl,imx8mp-media-blk-ctrl",
1899 #address-cells = <1>;
1900 #size-cells = <1>;
1901 power-domains = <&pgc_mediamix>,
1911 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1912 "lcdif1", "isi", "mipi-csi2",
1914 "mipi-dsi2";
1924 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
1935 clock-names = "apb", "axi", "cam1", "cam2",
1944 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1950 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1955 assigned-clock-rates = <500000000>, <200000000>,
1958 #power-domain-cells = <1>;
1961 compatible = "fsl,imx8mp-ldb";
1963 reg-names = "ldb", "lvds";
1965 clock-names = "ldb";
1966 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
1967 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
1971 #address-cells = <1>;
1972 #size-cells = <0>;
1978 remote-endpoint = <&lcdif2_to_ldb>;
1999 pcie_phy: pcie-phy@32f00000 {
2000 compatible = "fsl,imx8mp-pcie-phy";
2004 reset-names = "pciephy", "perst";
2005 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
2006 #phy-cells = <0>;
2010 hsio_blk_ctrl: blk-ctrl@32f10000 {
2011 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
2015 clock-names = "usb", "pcie";
2016 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
2019 power-domain-names = "bus", "usb", "usb-phy1",
2020 "usb-phy2", "pcie", "pcie-phy";
2025 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
2026 #power-domain-cells = <1>;
2027 #clock-cells = <0>;
2030 hdmi_blk_ctrl: blk-ctrl@32fc0000 {
2031 compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
2038 clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc";
2039 power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>,
2044 power-domain-names = "bus", "irqsteer", "lcdif",
2046 "hdmi-tx", "hdmi-tx-phy",
2048 #power-domain-cells = <1>;
2051 irqsteer_hdmi: interrupt-controller@32fc2000 {
2052 compatible = "fsl,imx8mp-irqsteer", "fsl,imx-irqsteer";
2055 interrupt-controller;
2056 #interrupt-cells = <1>;
2058 fsl,num-irqs = <64>;
2060 clock-names = "ipg";
2061 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>;
2064 hdmi_pvi: display-bridge@32fc4000 {
2065 compatible = "fsl,imx8mp-hdmi-pvi";
2067 interrupt-parent = <&irqsteer_hdmi>;
2069 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
2073 #address-cells = <1>;
2074 #size-cells = <0>;
2079 remote-endpoint = <&lcdif3_to_pvi>;
2086 remote-endpoint = <&hdmi_tx_from_pvi>;
2092 lcdif3: display-controller@32fc6000 {
2093 compatible = "fsl,imx8mp-lcdif";
2095 interrupt-parent = <&irqsteer_hdmi>;
2100 clock-names = "pix", "axi", "disp_axi";
2101 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>;
2106 remote-endpoint = <&pvi_from_lcdif3>;
2112 compatible = "fsl,imx8mp-hdmi-tx";
2114 interrupt-parent = <&irqsteer_hdmi>;
2120 clock-names = "iahb", "isfr", "cec", "pix";
2121 assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>;
2122 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
2123 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
2124 reg-io-width = <1>;
2128 #address-cells = <1>;
2129 #size-cells = <0>;
2135 remote-endpoint = <&pvi_to_hdmi_tx>;
2147 compatible = "fsl,imx8mp-hdmi-phy";
2151 clock-names = "apb", "ref";
2152 assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>;
2153 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2154 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
2155 #clock-cells = <0>;
2156 #phy-cells = <0>;
2162 compatible = "fsl,imx8mp-pcie";
2164 reg-names = "dbi", "config";
2168 clock-names = "pcie", "pcie_bus", "pcie_aux";
2169 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
2170 assigned-clock-rates = <10000000>;
2171 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
2172 #address-cells = <3>;
2173 #size-cells = <2>;
2175 bus-range = <0x00 0xff>;
2177 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
2178 num-lanes = <1>;
2179 num-viewport = <4>;
2181 interrupt-names = "msi";
2182 #interrupt-cells = <1>;
2183 interrupt-map-mask = <0 0 0 0x7>;
2184 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
2188 fsl,max-link-speed = <3>;
2189 linux,pci-domain = <0>;
2190 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
2193 reset-names = "apps", "turnoff";
2195 phy-names = "pcie-phy";
2199 pcie0_ep: pcie_ep: pcie-ep@33800000 {
2200 compatible = "fsl,imx8mp-pcie-ep";
2205 reg-names = "dbi", "addr_space", "dbi2", "atu";
2209 clock-names = "pcie", "pcie_bus", "pcie_aux";
2210 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
2211 assigned-clock-rates = <10000000>;
2212 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
2213 num-lanes = <1>;
2215 interrupt-names = "dma";
2216 fsl,max-link-speed = <3>;
2217 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
2220 reset-names = "apps", "turnoff";
2222 phy-names = "pcie-phy";
2223 num-ib-windows = <4>;
2224 num-ob-windows = <4>;
2236 clock-names = "core", "shader", "bus", "reg";
2237 #cooling-cells = <2>;
2238 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
2240 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
2242 assigned-clock-rates = <1000000000>, <1000000000>;
2243 power-domains = <&pgc_gpu3d>;
2253 clock-names = "core", "bus", "reg";
2254 #cooling-cells = <2>;
2255 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
2256 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
2257 assigned-clock-rates = <1000000000>;
2258 power-domains = <&pgc_gpu2d>;
2261 vpu_g1: video-codec@38300000 {
2262 compatible = "nxp,imx8mm-vpu-g1";
2266 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
2267 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
2268 assigned-clock-rates = <800000000>;
2269 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;
2272 vpu_g2: video-codec@38310000 {
2273 compatible = "nxp,imx8mq-vpu-g2";
2277 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_VPU_PLL_OUT>;
2278 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
2279 assigned-clock-rates = <700000000>, <700000000>;
2280 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;
2283 vpumix_blk_ctrl: blk-ctrl@38330000 {
2284 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
2286 #power-domain-cells = <1>;
2287 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
2289 power-domain-names = "bus", "g1", "g2", "vc8000e";
2293 clock-names = "g1", "g2", "vc8000e";
2294 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>;
2295 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
2296 assigned-clock-rates = <800000000>;
2300 interconnect-names = "g1", "g2", "vc8000e";
2311 clock-names = "core", "shader", "bus", "reg";
2312 #cooling-cells = <2>;
2313 power-domains = <&pgc_mlmix>;
2316 gic: interrupt-controller@38800000 {
2317 compatible = "arm,gic-v3";
2320 #interrupt-cells = <3>;
2321 interrupt-controller;
2323 interrupt-parent = <&gic>;
2326 edacmc: memory-controller@3d400000 {
2327 compatible = "snps,ddrc-3.80a";
2332 ddr-pmu@3d800000 {
2333 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
2338 usb3_phy0: usb-phy@381f0040 {
2339 compatible = "fsl,imx8mp-usb-phy";
2342 clock-names = "phy";
2343 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2344 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2345 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
2346 #phy-cells = <0>;
2351 compatible = "fsl,imx8mp-dwc3";
2356 clock-names = "hsio", "suspend";
2358 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2359 #address-cells = <1>;
2360 #size-cells = <1>;
2361 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2371 clock-names = "bus_early", "ref", "suspend";
2374 phy-names = "usb2-phy", "usb3-phy";
2375 snps,gfladj-refclk-lpm-sel-quirk;
2376 snps,parkmode-disable-ss-quirk;
2381 usb3_phy1: usb-phy@382f0040 {
2382 compatible = "fsl,imx8mp-usb-phy";
2385 clock-names = "phy";
2386 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2387 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2388 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
2389 #phy-cells = <0>;
2394 compatible = "fsl,imx8mp-dwc3";
2399 clock-names = "hsio", "suspend";
2401 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2402 #address-cells = <1>;
2403 #size-cells = <1>;
2404 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2414 clock-names = "bus_early", "ref", "suspend";
2417 phy-names = "usb2-phy", "usb3-phy";
2418 snps,gfladj-refclk-lpm-sel-quirk;
2419 snps,parkmode-disable-ss-quirk;
2424 compatible = "fsl,imx8mp-hifi4";
2430 clock-names = "ipg", "ocram", "core", "debug";
2431 power-domains = <&pgc_audio>;
2432 mbox-names = "tx", "rx", "rxdb";
2434 firmware-name = "imx/dsp/hifi4.bin";
2436 reset-names = "runstall";