Lines Matching +full:imx8mp +full:- +full:clock
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/reset/imx8mp-reset-audiomix.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/interconnect/fsl,imx8mp.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/thermal/thermal.h>
16 #include "imx8mp-aipstz.h"
17 #include "imx8mp-pinfunc.h"
20 interrupt-parent = <&gic>;
21 #address-cells = <2>;
22 #size-cells = <2>;
49 #address-cells = <1>;
50 #size-cells = <0>;
52 idle-states {
53 entry-method = "psci";
55 cpu_pd_wait: cpu-pd-wait {
56 compatible = "arm,idle-state";
57 arm,psci-suspend-param = <0x0010033>;
58 local-timer-stop;
59 entry-latency-us = <1000>;
60 exit-latency-us = <700>;
61 min-residency-us = <2700>;
62 wakeup-latency-us = <1500>;
68 compatible = "arm,cortex-a53";
71 enable-method = "psci";
72 i-cache-size = <0x8000>;
73 i-cache-line-size = <64>;
74 i-cache-sets = <256>;
75 d-cache-size = <0x8000>;
76 d-cache-line-size = <64>;
77 d-cache-sets = <128>;
78 next-level-cache = <&A53_L2>;
79 nvmem-cells = <&cpu_speed_grade>;
80 nvmem-cell-names = "speed_grade";
81 operating-points-v2 = <&a53_opp_table>;
82 #cooling-cells = <2>;
83 cpu-idle-states = <&cpu_pd_wait>;
85 cpu0_therm: thermal-idle {
86 #cooling-cells = <2>;
87 duration-us = <10000>;
88 exit-latency-us = <700>;
94 compatible = "arm,cortex-a53";
97 enable-method = "psci";
98 i-cache-size = <0x8000>;
99 i-cache-line-size = <64>;
100 i-cache-sets = <256>;
101 d-cache-size = <0x8000>;
102 d-cache-line-size = <64>;
103 d-cache-sets = <128>;
104 next-level-cache = <&A53_L2>;
105 operating-points-v2 = <&a53_opp_table>;
106 #cooling-cells = <2>;
107 cpu-idle-states = <&cpu_pd_wait>;
109 cpu1_therm: thermal-idle {
110 #cooling-cells = <2>;
111 duration-us = <10000>;
112 exit-latency-us = <700>;
118 compatible = "arm,cortex-a53";
121 enable-method = "psci";
122 i-cache-size = <0x8000>;
123 i-cache-line-size = <64>;
124 i-cache-sets = <256>;
125 d-cache-size = <0x8000>;
126 d-cache-line-size = <64>;
127 d-cache-sets = <128>;
128 next-level-cache = <&A53_L2>;
129 operating-points-v2 = <&a53_opp_table>;
130 #cooling-cells = <2>;
131 cpu-idle-states = <&cpu_pd_wait>;
133 cpu2_therm: thermal-idle {
134 #cooling-cells = <2>;
135 duration-us = <10000>;
136 exit-latency-us = <700>;
142 compatible = "arm,cortex-a53";
145 enable-method = "psci";
146 i-cache-size = <0x8000>;
147 i-cache-line-size = <64>;
148 i-cache-sets = <256>;
149 d-cache-size = <0x8000>;
150 d-cache-line-size = <64>;
151 d-cache-sets = <128>;
152 next-level-cache = <&A53_L2>;
153 operating-points-v2 = <&a53_opp_table>;
154 #cooling-cells = <2>;
155 cpu-idle-states = <&cpu_pd_wait>;
157 cpu3_therm: thermal-idle {
158 #cooling-cells = <2>;
159 duration-us = <10000>;
160 exit-latency-us = <700>;
164 A53_L2: l2-cache0 {
166 cache-unified;
167 cache-level = <2>;
168 cache-size = <0x80000>;
169 cache-line-size = <64>;
170 cache-sets = <512>;
174 a53_opp_table: opp-table {
175 compatible = "operating-points-v2";
176 opp-shared;
178 opp-1200000000 {
179 opp-hz = /bits/ 64 <1200000000>;
180 opp-microvolt = <850000>;
181 opp-supported-hw = <0x8a0>, <0x7>;
182 clock-latency-ns = <150000>;
183 opp-suspend;
186 opp-1600000000 {
187 opp-hz = /bits/ 64 <1600000000>;
188 opp-microvolt = <950000>;
189 opp-supported-hw = <0xa0>, <0x7>;
190 clock-latency-ns = <150000>;
191 opp-suspend;
194 opp-1800000000 {
195 opp-hz = /bits/ 64 <1800000000>;
196 opp-microvolt = <1000000>;
197 opp-supported-hw = <0x20>, <0x3>;
198 clock-latency-ns = <150000>;
199 opp-suspend;
203 osc_32k: clock-osc-32k {
204 compatible = "fixed-clock";
205 #clock-cells = <0>;
206 clock-frequency = <32768>;
207 clock-output-names = "osc_32k";
210 osc_24m: clock-osc-24m {
211 compatible = "fixed-clock";
212 #clock-cells = <0>;
213 clock-frequency = <24000000>;
214 clock-output-names = "osc_24m";
217 clk_ext1: clock-ext1 {
218 compatible = "fixed-clock";
219 #clock-cells = <0>;
220 clock-frequency = <133000000>;
221 clock-output-names = "clk_ext1";
224 clk_ext2: clock-ext2 {
225 compatible = "fixed-clock";
226 #clock-cells = <0>;
227 clock-frequency = <133000000>;
228 clock-output-names = "clk_ext2";
231 clk_ext3: clock-ext3 {
232 compatible = "fixed-clock";
233 #clock-cells = <0>;
234 clock-frequency = <133000000>;
235 clock-output-names = "clk_ext3";
238 clk_ext4: clock-ext4 {
239 compatible = "fixed-clock";
240 #clock-cells = <0>;
241 clock-frequency = <133000000>;
242 clock-output-names = "clk_ext4";
247 * non-configurable funnel don't show up on the AMBA
250 compatible = "arm,coresight-static-funnel";
252 in-ports {
253 #address-cells = <1>;
254 #size-cells = <0>;
260 remote-endpoint = <&etm0_out_port>;
268 remote-endpoint = <&etm1_out_port>;
276 remote-endpoint = <&etm2_out_port>;
284 remote-endpoint = <&etm3_out_port>;
289 out-ports {
293 remote-endpoint = <&hugo_funnel_in_port0>;
299 reserved-memory {
300 #address-cells = <2>;
301 #size-cells = <2>;
306 no-map;
312 compatible = "arm,cortex-a53-pmu";
318 compatible = "arm,psci-1.0";
322 thermal-zones {
323 cpu-thermal {
324 polling-delay-passive = <250>;
325 polling-delay = <2000>;
326 thermal-sensors = <&tmu 1>;
341 cooling-maps {
344 cooling-device =
360 soc-thermal {
361 polling-delay-passive = <250>;
362 polling-delay = <2000>;
363 thermal-sensors = <&tmu 0>;
378 cooling-maps {
381 cooling-device =
399 compatible = "arm,armv8-timer";
404 clock-frequency = <8000000>;
405 arm,no-tick-in-suspend;
409 compatible = "fsl,imx8mp-soc", "simple-bus";
410 #address-cells = <1>;
411 #size-cells = <1>;
413 nvmem-cells = <&imx8mp_uid>;
414 nvmem-cell-names = "soc_unique_id";
417 compatible = "arm,coresight-etm4x", "arm,primecell";
421 clock-names = "apb_pclk";
423 out-ports {
426 remote-endpoint = <&ca_funnel_in_port0>;
433 compatible = "arm,coresight-etm4x", "arm,primecell";
437 clock-names = "apb_pclk";
439 out-ports {
442 remote-endpoint = <&ca_funnel_in_port1>;
449 compatible = "arm,coresight-etm4x", "arm,primecell";
453 clock-names = "apb_pclk";
455 out-ports {
458 remote-endpoint = <&ca_funnel_in_port2>;
465 compatible = "arm,coresight-etm4x", "arm,primecell";
469 clock-names = "apb_pclk";
471 out-ports {
474 remote-endpoint = <&ca_funnel_in_port3>;
481 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
484 clock-names = "apb_pclk";
486 in-ports {
487 #address-cells = <1>;
488 #size-cells = <0>;
494 remote-endpoint = <&ca_funnel_out_port0>;
516 out-ports {
519 remote-endpoint = <&etf_in_port>;
526 compatible = "arm,coresight-tmc", "arm,primecell";
529 clock-names = "apb_pclk";
531 in-ports {
534 remote-endpoint = <&hugo_funnel_out_port0>;
539 out-ports {
542 remote-endpoint = <&etr_in_port>;
549 compatible = "arm,coresight-tmc", "arm,primecell";
552 clock-names = "apb_pclk";
554 in-ports {
557 remote-endpoint = <&etf_out_port>;
564 compatible = "fsl,aips-bus", "simple-bus";
566 #address-cells = <1>;
567 #size-cells = <1>;
571 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
576 gpio-controller;
577 #gpio-cells = <2>;
578 interrupt-controller;
579 #interrupt-cells = <2>;
580 gpio-ranges = <&iomuxc 0 5 30>;
584 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
589 gpio-controller;
590 #gpio-cells = <2>;
591 interrupt-controller;
592 #interrupt-cells = <2>;
593 gpio-ranges = <&iomuxc 0 35 21>;
597 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
602 gpio-controller;
603 #gpio-cells = <2>;
604 interrupt-controller;
605 #interrupt-cells = <2>;
606 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
610 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
615 gpio-controller;
616 #gpio-cells = <2>;
617 interrupt-controller;
618 #interrupt-cells = <2>;
619 gpio-ranges = <&iomuxc 0 82 32>;
623 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
628 gpio-controller;
629 #gpio-cells = <2>;
630 interrupt-controller;
631 #interrupt-cells = <2>;
632 gpio-ranges = <&iomuxc 0 114 30>;
636 compatible = "fsl,imx8mp-tmu";
639 nvmem-cells = <&tmu_calib>;
640 nvmem-cell-names = "calib";
641 #thermal-sensor-cells = <1>;
645 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
653 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
661 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
669 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
673 clock-names = "ipg", "per";
677 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
681 clock-names = "ipg", "per";
685 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
689 clock-names = "ipg", "per";
693 compatible = "fsl,imx8mp-iomuxc";
698 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
703 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
707 #address-cells = <1>;
708 #size-cells = <1>;
723 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
727 cpu_speed_grade: speed-grade@10 { /* 0x440 */
731 eth_mac1: mac-address@90 { /* 0x640 */
735 eth_mac2: mac-address@96 { /* 0x658 */
739 tmu_calib: calib@264 { /* 0xd90-0xdc0 */
744 anatop: clock-controller@30360000 {
745 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
747 #clock-cells = <1>;
751 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
754 snvs_rtc: snvs-rtc-lp {
755 compatible = "fsl,sec-v4.0-mon-rtc-lp";
761 clock-names = "snvs-rtc";
764 snvs_pwrkey: snvs-powerkey {
765 compatible = "fsl,sec-v4.0-pwrkey";
769 clock-names = "snvs-pwrkey";
771 wakeup-source;
775 snvs_lpgpr: snvs-lpgpr {
776 compatible = "fsl,imx8mp-snvs-lpgpr",
777 "fsl,imx7d-snvs-lpgpr";
781 clk: clock-controller@30380000 {
782 compatible = "fsl,imx8mp-ccm";
786 #clock-cells = <1>;
789 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
791 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
796 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
801 assigned-clock-rates = <0>, <0>,
807 src: reset-controller@30390000 {
808 compatible = "fsl,imx8mp-src", "syscon";
811 #reset-cells = <1>;
815 compatible = "fsl,imx8mp-gpc";
817 interrupt-parent = <&gic>;
819 interrupt-controller;
820 #interrupt-cells = <3>;
823 #address-cells = <1>;
824 #size-cells = <0>;
826 pgc_mipi_phy1: power-domain@0 {
827 #power-domain-cells = <0>;
831 pgc_pcie_phy: power-domain@1 {
832 #power-domain-cells = <0>;
836 pgc_usb1_phy: power-domain@2 {
837 #power-domain-cells = <0>;
841 pgc_usb2_phy: power-domain@3 {
842 #power-domain-cells = <0>;
846 pgc_mlmix: power-domain@4 {
847 #power-domain-cells = <0>;
852 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
855 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
858 assigned-clock-rates = <1000000000>,
863 pgc_audio: power-domain@5 {
864 #power-domain-cells = <0>;
868 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
870 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
872 assigned-clock-rates = <400000000>,
876 pgc_gpu2d: power-domain@6 {
877 #power-domain-cells = <0>;
880 power-domains = <&pgc_gpumix>;
883 pgc_gpumix: power-domain@7 {
884 #power-domain-cells = <0>;
888 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
890 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
892 assigned-clock-rates = <800000000>, <400000000>;
895 pgc_vpumix: power-domain@8 {
896 #power-domain-cells = <0>;
901 pgc_gpu3d: power-domain@9 {
902 #power-domain-cells = <0>;
906 power-domains = <&pgc_gpumix>;
909 pgc_mediamix: power-domain@10 {
910 #power-domain-cells = <0>;
916 pgc_vpu_g1: power-domain@11 {
917 #power-domain-cells = <0>;
921 pgc_vpu_g2: power-domain@12 {
922 #power-domain-cells = <0>;
926 pgc_vpu_vc8000e: power-domain@13 {
927 #power-domain-cells = <0>;
931 pgc_hdmimix: power-domain@14 {
932 #power-domain-cells = <0>;
936 assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
938 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
940 assigned-clock-rates = <500000000>, <133000000>;
943 pgc_hdmi_phy: power-domain@15 {
944 #power-domain-cells = <0>;
948 pgc_mipi_phy2: power-domain@16 {
949 #power-domain-cells = <0>;
953 pgc_hsiomix: power-domain@17 {
954 #power-domain-cells = <0>;
958 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
959 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
960 assigned-clock-rates = <500000000>;
963 pgc_ispdwp: power-domain@18 {
964 #power-domain-cells = <0>;
973 compatible = "fsl,aips-bus", "simple-bus";
975 #address-cells = <1>;
976 #size-cells = <1>;
980 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
985 clock-names = "ipg", "per";
986 #pwm-cells = <3>;
991 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
996 clock-names = "ipg", "per";
997 #pwm-cells = <3>;
1002 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
1007 clock-names = "ipg", "per";
1008 #pwm-cells = <3>;
1013 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
1018 clock-names = "ipg", "per";
1019 #pwm-cells = <3>;
1024 compatible = "nxp,sysctr-timer";
1028 clock-names = "per";
1032 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
1036 clock-names = "ipg", "per";
1040 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
1044 clock-names = "ipg", "per";
1048 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
1052 clock-names = "ipg", "per";
1057 compatible = "fsl,aips-bus", "simple-bus";
1059 #address-cells = <1>;
1060 #size-cells = <1>;
1063 spba-bus@30800000 {
1064 compatible = "fsl,spba-bus", "simple-bus";
1066 #address-cells = <1>;
1067 #size-cells = <1>;
1071 #address-cells = <1>;
1072 #size-cells = <0>;
1073 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1078 clock-names = "ipg", "per";
1079 assigned-clock-rates = <80000000>;
1080 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
1081 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1083 dma-names = "rx", "tx";
1088 #address-cells = <1>;
1089 #size-cells = <0>;
1090 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1095 clock-names = "ipg", "per";
1096 assigned-clock-rates = <80000000>;
1097 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
1098 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1100 dma-names = "rx", "tx";
1105 #address-cells = <1>;
1106 #size-cells = <0>;
1107 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1112 clock-names = "ipg", "per";
1113 assigned-clock-rates = <80000000>;
1114 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
1115 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1117 dma-names = "rx", "tx";
1122 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1127 clock-names = "ipg", "per";
1129 dma-names = "rx", "tx";
1134 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1139 clock-names = "ipg", "per";
1141 dma-names = "rx", "tx";
1146 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1151 clock-names = "ipg", "per";
1153 dma-names = "rx", "tx";
1158 compatible = "fsl,imx8mp-flexcan";
1163 clock-names = "ipg", "per";
1164 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
1165 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1166 assigned-clock-rates = <40000000>;
1167 fsl,clk-source = /bits/ 8 <0>;
1168 fsl,stop-mode = <&gpr 0x10 4>;
1173 compatible = "fsl,imx8mp-flexcan";
1178 clock-names = "ipg", "per";
1179 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
1180 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1181 assigned-clock-rates = <40000000>;
1182 fsl,clk-source = /bits/ 8 <0>;
1183 fsl,stop-mode = <&gpr 0x10 5>;
1189 compatible = "fsl,sec-v4.0";
1190 #address-cells = <1>;
1191 #size-cells = <1>;
1197 clock-names = "aclk", "ipg";
1200 compatible = "fsl,sec-v4.0-job-ring";
1207 compatible = "fsl,sec-v4.0-job-ring";
1213 compatible = "fsl,sec-v4.0-job-ring";
1220 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1221 #address-cells = <1>;
1222 #size-cells = <0>;
1230 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1231 #address-cells = <1>;
1232 #size-cells = <0>;
1240 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1241 #address-cells = <1>;
1242 #size-cells = <0>;
1250 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1251 #address-cells = <1>;
1252 #size-cells = <0>;
1260 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1265 clock-names = "ipg", "per";
1267 dma-names = "rx", "tx";
1272 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1276 #mbox-cells = <2>;
1280 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1283 #mbox-cells = <2>;
1289 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1290 #address-cells = <1>;
1291 #size-cells = <0>;
1299 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1309 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1315 clock-names = "ipg", "ahb", "per";
1316 fsl,tuning-start-tap = <20>;
1317 fsl,tuning-step = <2>;
1318 bus-width = <4>;
1323 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1329 clock-names = "ipg", "ahb", "per";
1330 fsl,tuning-start-tap = <20>;
1331 fsl,tuning-step = <2>;
1332 bus-width = <4>;
1337 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1343 clock-names = "ipg", "ahb", "per";
1344 fsl,tuning-start-tap = <20>;
1345 fsl,tuning-step = <2>;
1346 bus-width = <4>;
1351 compatible = "nxp,imx8mp-fspi";
1353 reg-names = "fspi_base", "fspi_mmap";
1357 clock-names = "fspi_en", "fspi";
1358 assigned-clock-rates = <80000000>;
1359 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
1360 #address-cells = <1>;
1361 #size-cells = <0>;
1365 sdma1: dma-controller@30bd0000 {
1366 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1371 clock-names = "ipg", "ahb";
1372 #dma-cells = <3>;
1373 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1377 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1388 clock-names = "ipg", "ahb", "ptp",
1390 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1394 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1398 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1399 fsl,num-tx-queues = <3>;
1400 fsl,num-rx-queues = <3>;
1401 nvmem-cells = <ð_mac1>;
1402 nvmem-cell-names = "mac-address";
1403 fsl,stop-mode = <&gpr 0x10 3>;
1408 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1412 interrupt-names = "macirq", "eth_wake_irq";
1417 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1418 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1421 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1424 assigned-clock-rates = <0>, <100000000>, <125000000>;
1425 nvmem-cells = <ð_mac2>;
1426 nvmem-cell-names = "mac-address";
1433 compatible = "fsl,imx8mp-aipstz";
1435 power-domains = <&pgc_audio>;
1436 #address-cells = <1>;
1437 #size-cells = <1>;
1438 #access-controller-cells = <3>;
1441 spba-bus@30c00000 {
1442 compatible = "fsl,spba-bus", "simple-bus";
1444 #address-cells = <1>;
1445 #size-cells = <1>;
1449 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1451 #sound-dai-cells = <0>;
1457 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1459 dma-names = "rx", "tx";
1465 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1467 #sound-dai-cells = <0>;
1473 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1475 dma-names = "rx", "tx";
1481 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1483 #sound-dai-cells = <0>;
1489 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1491 dma-names = "rx", "tx";
1497 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1499 #sound-dai-cells = <0>;
1505 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1507 dma-names = "rx", "tx";
1513 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1515 #sound-dai-cells = <0>;
1521 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1523 dma-names = "rx", "tx";
1529 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1531 #sound-dai-cells = <0>;
1537 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1539 dma-names = "rx", "tx";
1545 compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc";
1549 clock-names = "mem";
1554 dma-names = "ctx0_rx", "ctx0_tx",
1558 firmware-name = "imx/easrc/easrc-imx8mn.bin";
1559 fsl,asrc-rate = <8000>;
1560 fsl,asrc-format = <2>;
1564 micfil: audio-controller@30ca0000 {
1565 compatible = "fsl,imx8mp-micfil";
1567 #sound-dai-cells = <0>;
1577 clock-names = "ipg_clk", "ipg_clk_app",
1580 dma-names = "rx";
1585 compatible = "fsl,imx8mp-aud2htx";
1589 clock-names = "bus";
1591 dma-names = "tx";
1596 compatible = "fsl,imx8mp-xcvr";
1601 reg-names = "ram", "regs", "rxfifo",
1607 /* XCVR PHY - SPDIF wakeup IRQ */
1613 clock-names = "ipg", "phy", "spba", "pll_ipg";
1615 dma-names = "rx", "tx";
1621 sdma3: dma-controller@30e00000 {
1622 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1624 #dma-cells = <3>;
1627 clock-names = "ipg", "ahb";
1629 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1632 sdma2: dma-controller@30e10000 {
1633 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1635 #dma-cells = <3>;
1638 clock-names = "ipg", "ahb";
1640 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1643 audio_blk_ctrl: clock-controller@30e20000 {
1644 compatible = "fsl,imx8mp-audio-blk-ctrl";
1646 #clock-cells = <1>;
1647 #reset-cells = <1>;
1656 clock-names = "ahb",
1659 power-domains = <&pgc_audio>;
1660 assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>,
1662 assigned-clock-rates = <393216000>, <361267200>;
1667 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1670 #interconnect-cells = <1>;
1671 operating-points-v2 = <&noc_opp_table>;
1673 noc_opp_table: opp-table {
1674 compatible = "operating-points-v2";
1676 opp-200000000 {
1677 opp-hz = /bits/ 64 <200000000>;
1681 opp-800000000 {
1682 opp-hz = /bits/ 64 <800000000>;
1686 opp-1000000000 {
1687 opp-hz = /bits/ 64 <1000000000>;
1693 compatible = "fsl,aips-bus", "simple-bus";
1695 #address-cells = <1>;
1696 #size-cells = <1>;
1700 compatible = "fsl,imx8mp-isi";
1706 clock-names = "axi", "apb";
1707 fsl,blk-ctrl = <&media_blk_ctrl>;
1708 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
1712 #address-cells = <1>;
1713 #size-cells = <0>;
1719 remote-endpoint = <&mipi_csi_0_out>;
1727 remote-endpoint = <&mipi_csi_1_out>;
1734 compatible = "fsl,imx8mp-isp";
1741 clock-names = "isp", "aclk", "hclk", "pclk";
1742 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>,
1744 power-domain-names = "isp", "csi2";
1745 fsl,blk-ctrl = <&media_blk_ctrl 0>;
1749 #address-cells = <1>;
1750 #size-cells = <0>;
1759 compatible = "fsl,imx8mp-isp";
1766 clock-names = "isp", "aclk", "hclk", "pclk";
1767 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>,
1769 power-domain-names = "isp", "csi2";
1770 fsl,blk-ctrl = <&media_blk_ctrl 1>;
1774 #address-cells = <1>;
1775 #size-cells = <0>;
1784 compatible = "nxp,imx8mp-dw100";
1789 clock-names = "axi", "ahb";
1790 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
1794 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1797 clock-frequency = <250000000>;
1802 clock-names = "pclk", "wrap", "phy", "axi";
1803 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
1805 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
1807 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
1808 fsl,num-channels = <3>;
1812 #address-cells = <1>;
1813 #size-cells = <0>;
1823 remote-endpoint = <&isi_in_0>;
1830 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1833 clock-frequency = <250000000>;
1838 clock-names = "pclk", "wrap", "phy", "axi";
1839 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
1841 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
1843 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
1844 fsl,num-channels = <3>;
1848 #address-cells = <1>;
1849 #size-cells = <0>;
1859 remote-endpoint = <&isi_in_1>;
1866 compatible = "fsl,imx8mp-mipi-dsim";
1870 clock-names = "bus_clk", "sclk_mipi";
1871 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
1873 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1875 assigned-clock-rates = <200000000>, <24000000>;
1876 samsung,pll-clock-frequency = <24000000>;
1878 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
1882 #address-cells = <1>;
1883 #size-cells = <0>;
1889 remote-endpoint = <&lcdif1_to_dsim>;
1902 lcdif1: display-controller@32e80000 {
1903 compatible = "fsl,imx8mp-lcdif";
1908 clock-names = "pix", "axi", "disp_axi";
1910 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
1915 remote-endpoint = <&dsim_from_lcdif1>;
1920 lcdif2: display-controller@32e90000 {
1921 compatible = "fsl,imx8mp-lcdif";
1927 clock-names = "pix", "axi", "disp_axi";
1928 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;
1933 remote-endpoint = <&ldb_from_lcdif2>;
1938 media_blk_ctrl: blk-ctrl@32ec0000 {
1939 compatible = "fsl,imx8mp-media-blk-ctrl",
1942 #address-cells = <1>;
1943 #size-cells = <1>;
1944 power-domains = <&pgc_mediamix>,
1954 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1955 "lcdif1", "isi", "mipi-csi2",
1957 "mipi-dsi2";
1967 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
1978 clock-names = "apb", "axi", "cam1", "cam2",
1987 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1993 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1998 assigned-clock-rates = <500000000>, <200000000>,
2001 #power-domain-cells = <1>;
2004 compatible = "fsl,imx8mp-ldb";
2006 reg-names = "ldb", "lvds";
2008 clock-names = "ldb";
2009 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
2010 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
2014 #address-cells = <1>;
2015 #size-cells = <0>;
2021 remote-endpoint = <&lcdif2_to_ldb>;
2042 pcie_phy: pcie-phy@32f00000 {
2043 compatible = "fsl,imx8mp-pcie-phy";
2047 reset-names = "pciephy", "perst";
2048 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
2049 #phy-cells = <0>;
2053 hsio_blk_ctrl: blk-ctrl@32f10000 {
2054 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
2058 clock-names = "usb", "pcie";
2059 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
2062 power-domain-names = "bus", "usb", "usb-phy1",
2063 "usb-phy2", "pcie", "pcie-phy";
2068 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
2069 #power-domain-cells = <1>;
2070 #clock-cells = <0>;
2073 hdmi_blk_ctrl: blk-ctrl@32fc0000 {
2074 compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
2081 clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc";
2082 power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>,
2087 power-domain-names = "bus", "irqsteer", "lcdif",
2089 "hdmi-tx", "hdmi-tx-phy",
2094 interconnect-names = "hrv", "lcdif-hdmi", "hdcp";
2095 #power-domain-cells = <1>;
2098 irqsteer_hdmi: interrupt-controller@32fc2000 {
2099 compatible = "fsl,imx8mp-irqsteer", "fsl,imx-irqsteer";
2102 interrupt-controller;
2103 #interrupt-cells = <1>;
2105 fsl,num-irqs = <64>;
2107 clock-names = "ipg";
2108 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>;
2111 hdmi_pvi: display-bridge@32fc4000 {
2112 compatible = "fsl,imx8mp-hdmi-pvi";
2114 interrupt-parent = <&irqsteer_hdmi>;
2116 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
2120 #address-cells = <1>;
2121 #size-cells = <0>;
2126 remote-endpoint = <&lcdif3_to_pvi>;
2133 remote-endpoint = <&hdmi_tx_from_pvi>;
2139 hdmi_pai: audio-bridge@32fc4800 {
2140 compatible = "fsl,imx8mp-hdmi-pai";
2142 interrupt-parent = <&irqsteer_hdmi>;
2145 clock-names = "apb";
2146 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PAI>;
2151 remote-endpoint = <&hdmi_tx_from_pai>;
2156 lcdif3: display-controller@32fc6000 {
2157 compatible = "fsl,imx8mp-lcdif";
2159 interrupt-parent = <&irqsteer_hdmi>;
2164 clock-names = "pix", "axi", "disp_axi";
2165 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>;
2170 remote-endpoint = <&pvi_from_lcdif3>;
2176 compatible = "fsl,imx8mp-hdmi-tx";
2178 interrupt-parent = <&irqsteer_hdmi>;
2184 clock-names = "iahb", "isfr", "cec", "pix";
2185 assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>;
2186 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
2187 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
2188 reg-io-width = <1>;
2192 #address-cells = <1>;
2193 #size-cells = <0>;
2199 remote-endpoint = <&pvi_to_hdmi_tx>;
2212 remote-endpoint = <&pai_to_hdmi_tx>;
2219 compatible = "fsl,imx8mp-hdmi-phy";
2223 clock-names = "apb", "ref";
2224 assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>;
2225 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2226 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
2227 #clock-cells = <0>;
2228 #phy-cells = <0>;
2234 compatible = "fsl,imx8mp-pcie";
2236 reg-names = "dbi", "config";
2240 clock-names = "pcie", "pcie_bus", "pcie_aux";
2241 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
2242 assigned-clock-rates = <10000000>;
2243 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
2244 #address-cells = <3>;
2245 #size-cells = <2>;
2247 bus-range = <0x00 0xff>;
2249 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
2250 num-lanes = <1>;
2251 num-viewport = <4>;
2253 interrupt-names = "msi";
2254 #interrupt-cells = <1>;
2255 interrupt-map-mask = <0 0 0 0x7>;
2256 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
2260 fsl,max-link-speed = <3>;
2261 linux,pci-domain = <0>;
2262 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
2265 reset-names = "apps", "turnoff";
2267 phy-names = "pcie-phy";
2271 pcie0_ep: pcie_ep: pcie-ep@33800000 {
2272 compatible = "fsl,imx8mp-pcie-ep";
2277 reg-names = "dbi", "addr_space", "dbi2", "atu";
2281 clock-names = "pcie", "pcie_bus", "pcie_aux";
2282 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
2283 assigned-clock-rates = <10000000>;
2284 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
2285 num-lanes = <1>;
2287 interrupt-names = "dma";
2288 fsl,max-link-speed = <3>;
2289 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
2292 reset-names = "apps", "turnoff";
2294 phy-names = "pcie-phy";
2295 num-ib-windows = <4>;
2296 num-ob-windows = <4>;
2308 clock-names = "core", "shader", "bus", "reg";
2309 #cooling-cells = <2>;
2310 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
2312 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
2314 assigned-clock-rates = <1000000000>, <1000000000>;
2315 power-domains = <&pgc_gpu3d>;
2325 clock-names = "core", "bus", "reg";
2326 #cooling-cells = <2>;
2327 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
2328 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
2329 assigned-clock-rates = <1000000000>;
2330 power-domains = <&pgc_gpu2d>;
2333 vpu_g1: video-codec@38300000 {
2334 compatible = "nxp,imx8mm-vpu-g1";
2338 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
2339 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
2340 assigned-clock-rates = <800000000>;
2341 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;
2344 vpu_g2: video-codec@38310000 {
2345 compatible = "nxp,imx8mq-vpu-g2";
2349 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_VPU_PLL_OUT>;
2350 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
2351 assigned-clock-rates = <700000000>, <700000000>;
2352 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;
2355 vpumix_blk_ctrl: blk-ctrl@38330000 {
2356 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
2358 #power-domain-cells = <1>;
2359 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
2361 power-domain-names = "bus", "g1", "g2", "vc8000e";
2365 clock-names = "g1", "g2", "vc8000e";
2366 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>;
2367 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
2368 assigned-clock-rates = <800000000>;
2372 interconnect-names = "g1", "g2", "vc8000e";
2383 clock-names = "core", "shader", "bus", "reg";
2384 #cooling-cells = <2>;
2385 power-domains = <&pgc_mlmix>;
2388 gic: interrupt-controller@38800000 {
2389 compatible = "arm,gic-v3";
2392 #address-cells = <0>;
2393 #interrupt-cells = <3>;
2394 interrupt-controller;
2396 interrupt-parent = <&gic>;
2399 edacmc: memory-controller@3d400000 {
2400 compatible = "snps,ddrc-3.80a";
2405 ddr-pmu@3d800000 {
2406 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
2411 usb3_phy0: usb-phy@381f0040 {
2412 compatible = "fsl,imx8mp-usb-phy";
2415 clock-names = "phy";
2416 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2417 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2418 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
2419 #phy-cells = <0>;
2424 compatible = "fsl,imx8mp-dwc3";
2429 clock-names = "hsio", "suspend";
2431 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2432 #address-cells = <1>;
2433 #size-cells = <1>;
2434 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2444 clock-names = "bus_early", "ref", "suspend";
2447 phy-names = "usb2-phy", "usb3-phy";
2448 snps,gfladj-refclk-lpm-sel-quirk;
2449 snps,parkmode-disable-ss-quirk;
2454 usb3_phy1: usb-phy@382f0040 {
2455 compatible = "fsl,imx8mp-usb-phy";
2458 clock-names = "phy";
2459 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2460 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2461 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
2462 #phy-cells = <0>;
2467 compatible = "fsl,imx8mp-dwc3";
2472 clock-names = "hsio", "suspend";
2474 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2475 #address-cells = <1>;
2476 #size-cells = <1>;
2477 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2487 clock-names = "bus_early", "ref", "suspend";
2490 phy-names = "usb2-phy", "usb3-phy";
2491 snps,gfladj-refclk-lpm-sel-quirk;
2492 snps,parkmode-disable-ss-quirk;
2497 compatible = "fsl,imx8mp-hifi4";
2503 clock-names = "ipg", "ocram", "core", "debug";
2504 power-domains = <&pgc_audio>;
2505 mbox-names = "tx", "rx", "rxdb";
2507 firmware-name = "imx/dsp/hifi4.bin";
2509 reset-names = "runstall";
2510 access-controllers = <&aips5