Lines Matching +full:aips +full:- +full:bus
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
47 #address-cells = <1>;
48 #size-cells = <0>;
50 idle-states {
51 entry-method = "psci";
53 cpu_pd_wait: cpu-pd-wait {
54 compatible = "arm,idle-state";
55 arm,psci-suspend-param = <0x0010033>;
56 local-timer-stop;
57 entry-latency-us = <1000>;
58 exit-latency-us = <700>;
59 min-residency-us = <2700>;
60 wakeup-latency-us = <1500>;
66 compatible = "arm,cortex-a53";
68 clock-latency = <61036>;
70 enable-method = "psci";
71 i-cache-size = <0x8000>;
72 i-cache-line-size = <64>;
73 i-cache-sets = <256>;
74 d-cache-size = <0x8000>;
75 d-cache-line-size = <64>;
76 d-cache-sets = <128>;
77 next-level-cache = <&A53_L2>;
78 nvmem-cells = <&cpu_speed_grade>;
79 nvmem-cell-names = "speed_grade";
80 operating-points-v2 = <&a53_opp_table>;
81 #cooling-cells = <2>;
82 cpu-idle-states = <&cpu_pd_wait>;
87 compatible = "arm,cortex-a53";
89 clock-latency = <61036>;
91 enable-method = "psci";
92 i-cache-size = <0x8000>;
93 i-cache-line-size = <64>;
94 i-cache-sets = <256>;
95 d-cache-size = <0x8000>;
96 d-cache-line-size = <64>;
97 d-cache-sets = <128>;
98 next-level-cache = <&A53_L2>;
99 operating-points-v2 = <&a53_opp_table>;
100 #cooling-cells = <2>;
101 cpu-idle-states = <&cpu_pd_wait>;
106 compatible = "arm,cortex-a53";
108 clock-latency = <61036>;
110 enable-method = "psci";
111 i-cache-size = <0x8000>;
112 i-cache-line-size = <64>;
113 i-cache-sets = <256>;
114 d-cache-size = <0x8000>;
115 d-cache-line-size = <64>;
116 d-cache-sets = <128>;
117 next-level-cache = <&A53_L2>;
118 operating-points-v2 = <&a53_opp_table>;
119 #cooling-cells = <2>;
120 cpu-idle-states = <&cpu_pd_wait>;
125 compatible = "arm,cortex-a53";
127 clock-latency = <61036>;
129 enable-method = "psci";
130 i-cache-size = <0x8000>;
131 i-cache-line-size = <64>;
132 i-cache-sets = <256>;
133 d-cache-size = <0x8000>;
134 d-cache-line-size = <64>;
135 d-cache-sets = <128>;
136 next-level-cache = <&A53_L2>;
137 operating-points-v2 = <&a53_opp_table>;
138 #cooling-cells = <2>;
139 cpu-idle-states = <&cpu_pd_wait>;
142 A53_L2: l2-cache0 {
144 cache-unified;
145 cache-level = <2>;
146 cache-size = <0x80000>;
147 cache-line-size = <64>;
148 cache-sets = <512>;
152 a53_opp_table: opp-table {
153 compatible = "operating-points-v2";
154 opp-shared;
156 opp-1200000000 {
157 opp-hz = /bits/ 64 <1200000000>;
158 opp-microvolt = <850000>;
159 opp-supported-hw = <0x8a0>, <0x7>;
160 clock-latency-ns = <150000>;
161 opp-suspend;
164 opp-1600000000 {
165 opp-hz = /bits/ 64 <1600000000>;
166 opp-microvolt = <950000>;
167 opp-supported-hw = <0xa0>, <0x7>;
168 clock-latency-ns = <150000>;
169 opp-suspend;
172 opp-1800000000 {
173 opp-hz = /bits/ 64 <1800000000>;
174 opp-microvolt = <1000000>;
175 opp-supported-hw = <0x20>, <0x3>;
176 clock-latency-ns = <150000>;
177 opp-suspend;
181 osc_32k: clock-osc-32k {
182 compatible = "fixed-clock";
183 #clock-cells = <0>;
184 clock-frequency = <32768>;
185 clock-output-names = "osc_32k";
188 osc_24m: clock-osc-24m {
189 compatible = "fixed-clock";
190 #clock-cells = <0>;
191 clock-frequency = <24000000>;
192 clock-output-names = "osc_24m";
195 clk_ext1: clock-ext1 {
196 compatible = "fixed-clock";
197 #clock-cells = <0>;
198 clock-frequency = <133000000>;
199 clock-output-names = "clk_ext1";
202 clk_ext2: clock-ext2 {
203 compatible = "fixed-clock";
204 #clock-cells = <0>;
205 clock-frequency = <133000000>;
206 clock-output-names = "clk_ext2";
209 clk_ext3: clock-ext3 {
210 compatible = "fixed-clock";
211 #clock-cells = <0>;
212 clock-frequency = <133000000>;
213 clock-output-names = "clk_ext3";
216 clk_ext4: clock-ext4 {
217 compatible = "fixed-clock";
218 #clock-cells = <0>;
219 clock-frequency = <133000000>;
220 clock-output-names = "clk_ext4";
225 * non-configurable funnel don't show up on the AMBA
226 * bus. As such no need to add "arm,primecell".
228 compatible = "arm,coresight-static-funnel";
230 in-ports {
231 #address-cells = <1>;
232 #size-cells = <0>;
238 remote-endpoint = <&etm0_out_port>;
246 remote-endpoint = <&etm1_out_port>;
254 remote-endpoint = <&etm2_out_port>;
262 remote-endpoint = <&etm3_out_port>;
267 out-ports {
271 remote-endpoint = <&hugo_funnel_in_port0>;
277 reserved-memory {
278 #address-cells = <2>;
279 #size-cells = <2>;
284 no-map;
290 compatible = "arm,cortex-a53-pmu";
296 compatible = "arm,psci-1.0";
300 thermal-zones {
301 cpu-thermal {
302 polling-delay-passive = <250>;
303 polling-delay = <2000>;
304 thermal-sensors = <&tmu 0>;
319 cooling-maps {
322 cooling-device =
331 soc-thermal {
332 polling-delay-passive = <250>;
333 polling-delay = <2000>;
334 thermal-sensors = <&tmu 1>;
349 cooling-maps {
352 cooling-device =
363 compatible = "arm,armv8-timer";
368 clock-frequency = <8000000>;
369 arm,no-tick-in-suspend;
373 compatible = "fsl,imx8mp-soc", "simple-bus";
374 #address-cells = <1>;
375 #size-cells = <1>;
377 nvmem-cells = <&imx8mp_uid>;
378 nvmem-cell-names = "soc_unique_id";
381 compatible = "arm,coresight-etm4x", "arm,primecell";
385 clock-names = "apb_pclk";
387 out-ports {
390 remote-endpoint = <&ca_funnel_in_port0>;
397 compatible = "arm,coresight-etm4x", "arm,primecell";
401 clock-names = "apb_pclk";
403 out-ports {
406 remote-endpoint = <&ca_funnel_in_port1>;
413 compatible = "arm,coresight-etm4x", "arm,primecell";
417 clock-names = "apb_pclk";
419 out-ports {
422 remote-endpoint = <&ca_funnel_in_port2>;
429 compatible = "arm,coresight-etm4x", "arm,primecell";
433 clock-names = "apb_pclk";
435 out-ports {
438 remote-endpoint = <&ca_funnel_in_port3>;
445 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
448 clock-names = "apb_pclk";
450 in-ports {
451 #address-cells = <1>;
452 #size-cells = <0>;
458 remote-endpoint = <&ca_funnel_out_port0>;
480 out-ports {
483 remote-endpoint = <&etf_in_port>;
490 compatible = "arm,coresight-tmc", "arm,primecell";
493 clock-names = "apb_pclk";
495 in-ports {
498 remote-endpoint = <&hugo_funnel_out_port0>;
503 out-ports {
506 remote-endpoint = <&etr_in_port>;
513 compatible = "arm,coresight-tmc", "arm,primecell";
516 clock-names = "apb_pclk";
518 in-ports {
521 remote-endpoint = <&etf_out_port>;
527 aips1: bus@30000000 {
528 compatible = "fsl,aips-bus", "simple-bus";
530 #address-cells = <1>;
531 #size-cells = <1>;
535 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
540 gpio-controller;
541 #gpio-cells = <2>;
542 interrupt-controller;
543 #interrupt-cells = <2>;
544 gpio-ranges = <&iomuxc 0 5 30>;
548 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
553 gpio-controller;
554 #gpio-cells = <2>;
555 interrupt-controller;
556 #interrupt-cells = <2>;
557 gpio-ranges = <&iomuxc 0 35 21>;
561 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
566 gpio-controller;
567 #gpio-cells = <2>;
568 interrupt-controller;
569 #interrupt-cells = <2>;
570 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
574 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
579 gpio-controller;
580 #gpio-cells = <2>;
581 interrupt-controller;
582 #interrupt-cells = <2>;
583 gpio-ranges = <&iomuxc 0 82 32>;
587 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
592 gpio-controller;
593 #gpio-cells = <2>;
594 interrupt-controller;
595 #interrupt-cells = <2>;
596 gpio-ranges = <&iomuxc 0 114 30>;
600 compatible = "fsl,imx8mp-tmu";
603 nvmem-cells = <&tmu_calib>;
604 nvmem-cell-names = "calib";
605 #thermal-sensor-cells = <1>;
609 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
617 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
625 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
633 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
637 clock-names = "ipg", "per";
641 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
645 clock-names = "ipg", "per";
649 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
653 clock-names = "ipg", "per";
657 compatible = "fsl,imx8mp-iomuxc";
662 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
667 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
671 #address-cells = <1>;
672 #size-cells = <1>;
687 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
691 cpu_speed_grade: speed-grade@10 { /* 0x440 */
695 eth_mac1: mac-address@90 { /* 0x640 */
699 eth_mac2: mac-address@96 { /* 0x658 */
703 tmu_calib: calib@264 { /* 0xd90-0xdc0 */
708 anatop: clock-controller@30360000 {
709 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
711 #clock-cells = <1>;
715 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
718 snvs_rtc: snvs-rtc-lp {
719 compatible = "fsl,sec-v4.0-mon-rtc-lp";
725 clock-names = "snvs-rtc";
728 snvs_pwrkey: snvs-powerkey {
729 compatible = "fsl,sec-v4.0-pwrkey";
733 clock-names = "snvs-pwrkey";
735 wakeup-source;
739 snvs_lpgpr: snvs-lpgpr {
740 compatible = "fsl,imx8mp-snvs-lpgpr",
741 "fsl,imx7d-snvs-lpgpr";
745 clk: clock-controller@30380000 {
746 compatible = "fsl,imx8mp-ccm";
750 #clock-cells = <1>;
753 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
755 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
760 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
765 assigned-clock-rates = <0>, <0>,
771 src: reset-controller@30390000 {
772 compatible = "fsl,imx8mp-src", "syscon";
775 #reset-cells = <1>;
779 compatible = "fsl,imx8mp-gpc";
781 interrupt-parent = <&gic>;
783 interrupt-controller;
784 #interrupt-cells = <3>;
787 #address-cells = <1>;
788 #size-cells = <0>;
790 pgc_mipi_phy1: power-domain@0 {
791 #power-domain-cells = <0>;
795 pgc_pcie_phy: power-domain@1 {
796 #power-domain-cells = <0>;
800 pgc_usb1_phy: power-domain@2 {
801 #power-domain-cells = <0>;
805 pgc_usb2_phy: power-domain@3 {
806 #power-domain-cells = <0>;
810 pgc_mlmix: power-domain@4 {
811 #power-domain-cells = <0>;
816 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
819 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
822 assigned-clock-rates = <800000000>,
827 pgc_audio: power-domain@5 {
828 #power-domain-cells = <0>;
832 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
834 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
836 assigned-clock-rates = <400000000>,
840 pgc_gpu2d: power-domain@6 {
841 #power-domain-cells = <0>;
844 power-domains = <&pgc_gpumix>;
847 pgc_gpumix: power-domain@7 {
848 #power-domain-cells = <0>;
852 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
854 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
856 assigned-clock-rates = <800000000>, <400000000>;
859 pgc_vpumix: power-domain@8 {
860 #power-domain-cells = <0>;
865 pgc_gpu3d: power-domain@9 {
866 #power-domain-cells = <0>;
870 power-domains = <&pgc_gpumix>;
873 pgc_mediamix: power-domain@10 {
874 #power-domain-cells = <0>;
880 pgc_vpu_g1: power-domain@11 {
881 #power-domain-cells = <0>;
882 power-domains = <&pgc_vpumix>;
887 pgc_vpu_g2: power-domain@12 {
888 #power-domain-cells = <0>;
889 power-domains = <&pgc_vpumix>;
895 pgc_vpu_vc8000e: power-domain@13 {
896 #power-domain-cells = <0>;
897 power-domains = <&pgc_vpumix>;
902 pgc_hdmimix: power-domain@14 {
903 #power-domain-cells = <0>;
907 assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
909 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
911 assigned-clock-rates = <500000000>, <133000000>;
914 pgc_hdmi_phy: power-domain@15 {
915 #power-domain-cells = <0>;
919 pgc_mipi_phy2: power-domain@16 {
920 #power-domain-cells = <0>;
924 pgc_hsiomix: power-domain@17 {
925 #power-domain-cells = <0>;
929 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
930 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
931 assigned-clock-rates = <500000000>;
934 pgc_ispdwp: power-domain@18 {
935 #power-domain-cells = <0>;
943 aips2: bus@30400000 {
944 compatible = "fsl,aips-bus", "simple-bus";
946 #address-cells = <1>;
947 #size-cells = <1>;
951 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
956 clock-names = "ipg", "per";
957 #pwm-cells = <3>;
962 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
967 clock-names = "ipg", "per";
968 #pwm-cells = <3>;
973 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
978 clock-names = "ipg", "per";
979 #pwm-cells = <3>;
984 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
989 clock-names = "ipg", "per";
990 #pwm-cells = <3>;
995 compatible = "nxp,sysctr-timer";
999 clock-names = "per";
1003 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
1007 clock-names = "ipg", "per";
1011 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
1015 clock-names = "ipg", "per";
1019 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
1023 clock-names = "ipg", "per";
1027 aips3: bus@30800000 {
1028 compatible = "fsl,aips-bus", "simple-bus";
1030 #address-cells = <1>;
1031 #size-cells = <1>;
1034 spba-bus@30800000 {
1035 compatible = "fsl,spba-bus", "simple-bus";
1037 #address-cells = <1>;
1038 #size-cells = <1>;
1042 #address-cells = <1>;
1043 #size-cells = <0>;
1044 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1049 clock-names = "ipg", "per";
1050 assigned-clock-rates = <80000000>;
1051 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
1052 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1054 dma-names = "rx", "tx";
1059 #address-cells = <1>;
1060 #size-cells = <0>;
1061 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1066 clock-names = "ipg", "per";
1067 assigned-clock-rates = <80000000>;
1068 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
1069 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1071 dma-names = "rx", "tx";
1076 #address-cells = <1>;
1077 #size-cells = <0>;
1078 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1083 clock-names = "ipg", "per";
1084 assigned-clock-rates = <80000000>;
1085 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
1086 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1088 dma-names = "rx", "tx";
1093 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1098 clock-names = "ipg", "per";
1100 dma-names = "rx", "tx";
1105 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1110 clock-names = "ipg", "per";
1112 dma-names = "rx", "tx";
1117 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1122 clock-names = "ipg", "per";
1124 dma-names = "rx", "tx";
1129 compatible = "fsl,imx8mp-flexcan";
1134 clock-names = "ipg", "per";
1135 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
1136 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1137 assigned-clock-rates = <40000000>;
1138 fsl,clk-source = /bits/ 8 <0>;
1139 fsl,stop-mode = <&gpr 0x10 4>;
1144 compatible = "fsl,imx8mp-flexcan";
1149 clock-names = "ipg", "per";
1150 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
1151 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1152 assigned-clock-rates = <40000000>;
1153 fsl,clk-source = /bits/ 8 <0>;
1154 fsl,stop-mode = <&gpr 0x10 5>;
1160 compatible = "fsl,sec-v4.0";
1161 #address-cells = <1>;
1162 #size-cells = <1>;
1168 clock-names = "aclk", "ipg";
1171 compatible = "fsl,sec-v4.0-job-ring";
1178 compatible = "fsl,sec-v4.0-job-ring";
1184 compatible = "fsl,sec-v4.0-job-ring";
1191 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1192 #address-cells = <1>;
1193 #size-cells = <0>;
1201 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1202 #address-cells = <1>;
1203 #size-cells = <0>;
1211 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1212 #address-cells = <1>;
1213 #size-cells = <0>;
1221 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1222 #address-cells = <1>;
1223 #size-cells = <0>;
1231 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1236 clock-names = "ipg", "per";
1238 dma-names = "rx", "tx";
1243 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1247 #mbox-cells = <2>;
1251 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1254 #mbox-cells = <2>;
1259 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1260 #address-cells = <1>;
1261 #size-cells = <0>;
1269 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1270 #address-cells = <1>;
1271 #size-cells = <0>;
1279 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1285 clock-names = "ipg", "ahb", "per";
1286 fsl,tuning-start-tap = <20>;
1287 fsl,tuning-step = <2>;
1288 bus-width = <4>;
1293 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1299 clock-names = "ipg", "ahb", "per";
1300 fsl,tuning-start-tap = <20>;
1301 fsl,tuning-step = <2>;
1302 bus-width = <4>;
1307 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1313 clock-names = "ipg", "ahb", "per";
1314 fsl,tuning-start-tap = <20>;
1315 fsl,tuning-step = <2>;
1316 bus-width = <4>;
1321 compatible = "nxp,imx8mp-fspi";
1323 reg-names = "fspi_base", "fspi_mmap";
1327 clock-names = "fspi_en", "fspi";
1328 assigned-clock-rates = <80000000>;
1329 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
1330 #address-cells = <1>;
1331 #size-cells = <0>;
1335 sdma1: dma-controller@30bd0000 {
1336 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1341 clock-names = "ipg", "ahb";
1342 #dma-cells = <3>;
1343 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1347 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1358 clock-names = "ipg", "ahb", "ptp",
1360 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1364 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1368 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1369 fsl,num-tx-queues = <3>;
1370 fsl,num-rx-queues = <3>;
1371 nvmem-cells = <ð_mac1>;
1372 nvmem-cell-names = "mac-address";
1373 fsl,stop-mode = <&gpr 0x10 3>;
1378 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1382 interrupt-names = "macirq", "eth_wake_irq";
1387 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1388 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1391 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1394 assigned-clock-rates = <0>, <100000000>, <125000000>;
1395 nvmem-cells = <ð_mac2>;
1396 nvmem-cell-names = "mac-address";
1402 aips5: bus@30c00000 {
1403 compatible = "fsl,aips-bus", "simple-bus";
1405 #address-cells = <1>;
1406 #size-cells = <1>;
1409 spba-bus@30c00000 {
1410 compatible = "fsl,spba-bus", "simple-bus";
1412 #address-cells = <1>;
1413 #size-cells = <1>;
1417 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1419 #sound-dai-cells = <0>;
1425 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1427 dma-names = "rx", "tx";
1433 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1435 #sound-dai-cells = <0>;
1441 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1443 dma-names = "rx", "tx";
1449 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1451 #sound-dai-cells = <0>;
1457 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1459 dma-names = "rx", "tx";
1465 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1467 #sound-dai-cells = <0>;
1473 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1475 dma-names = "rx", "tx";
1481 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1483 #sound-dai-cells = <0>;
1489 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1491 dma-names = "rx", "tx";
1497 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1499 #sound-dai-cells = <0>;
1505 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1507 dma-names = "rx", "tx";
1513 compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc";
1517 clock-names = "mem";
1522 dma-names = "ctx0_rx", "ctx0_tx",
1526 firmware-name = "imx/easrc/easrc-imx8mn.bin";
1527 fsl,asrc-rate = <8000>;
1528 fsl,asrc-format = <2>;
1532 micfil: audio-controller@30ca0000 {
1533 compatible = "fsl,imx8mp-micfil";
1535 #sound-dai-cells = <0>;
1545 clock-names = "ipg_clk", "ipg_clk_app",
1548 dma-names = "rx";
1553 compatible = "fsl,imx8mp-aud2htx";
1557 clock-names = "bus";
1559 dma-names = "tx";
1564 compatible = "fsl,imx8mp-xcvr";
1569 reg-names = "ram", "regs", "rxfifo",
1575 /* XCVR PHY - SPDIF wakeup IRQ */
1581 clock-names = "ipg", "phy", "spba", "pll_ipg";
1583 dma-names = "rx", "tx";
1589 sdma3: dma-controller@30e00000 {
1590 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1592 #dma-cells = <3>;
1595 clock-names = "ipg", "ahb";
1597 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1600 sdma2: dma-controller@30e10000 {
1601 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1603 #dma-cells = <3>;
1606 clock-names = "ipg", "ahb";
1608 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1611 audio_blk_ctrl: clock-controller@30e20000 {
1612 compatible = "fsl,imx8mp-audio-blk-ctrl";
1614 #clock-cells = <1>;
1615 #reset-cells = <1>;
1623 clock-names = "ahb",
1626 power-domains = <&pgc_audio>;
1627 assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>,
1629 assigned-clock-rates = <393216000>, <361267200>;
1634 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1637 #interconnect-cells = <1>;
1638 operating-points-v2 = <&noc_opp_table>;
1640 noc_opp_table: opp-table {
1641 compatible = "operating-points-v2";
1643 opp-200000000 {
1644 opp-hz = /bits/ 64 <200000000>;
1647 opp-1000000000 {
1648 opp-hz = /bits/ 64 <1000000000>;
1653 aips4: bus@32c00000 {
1654 compatible = "fsl,aips-bus", "simple-bus";
1656 #address-cells = <1>;
1657 #size-cells = <1>;
1661 compatible = "fsl,imx8mp-isi";
1667 clock-names = "axi", "apb";
1668 fsl,blk-ctrl = <&media_blk_ctrl>;
1669 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
1673 #address-cells = <1>;
1674 #size-cells = <0>;
1680 remote-endpoint = <&mipi_csi_0_out>;
1688 remote-endpoint = <&mipi_csi_1_out>;
1695 compatible = "fsl,imx8mp-isp";
1701 clock-names = "isp", "aclk", "hclk";
1702 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
1703 fsl,blk-ctrl = <&media_blk_ctrl 0>;
1707 #address-cells = <1>;
1708 #size-cells = <0>;
1717 compatible = "fsl,imx8mp-isp";
1723 clock-names = "isp", "aclk", "hclk";
1724 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
1725 fsl,blk-ctrl = <&media_blk_ctrl 1>;
1729 #address-cells = <1>;
1730 #size-cells = <0>;
1739 compatible = "nxp,imx8mp-dw100";
1744 clock-names = "axi", "ahb";
1745 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
1749 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1752 clock-frequency = <250000000>;
1757 clock-names = "pclk", "wrap", "phy", "axi";
1758 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
1760 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
1762 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
1766 #address-cells = <1>;
1767 #size-cells = <0>;
1777 remote-endpoint = <&isi_in_0>;
1784 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1787 clock-frequency = <250000000>;
1792 clock-names = "pclk", "wrap", "phy", "axi";
1793 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
1795 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
1797 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
1801 #address-cells = <1>;
1802 #size-cells = <0>;
1812 remote-endpoint = <&isi_in_1>;
1819 compatible = "fsl,imx8mp-mipi-dsim";
1823 clock-names = "bus_clk", "sclk_mipi";
1824 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
1826 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1828 assigned-clock-rates = <200000000>, <24000000>;
1829 samsung,pll-clock-frequency = <24000000>;
1831 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
1835 #address-cells = <1>;
1836 #size-cells = <0>;
1842 remote-endpoint = <&lcdif1_to_dsim>;
1855 lcdif1: display-controller@32e80000 {
1856 compatible = "fsl,imx8mp-lcdif";
1861 clock-names = "pix", "axi", "disp_axi";
1863 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
1868 remote-endpoint = <&dsim_from_lcdif1>;
1873 lcdif2: display-controller@32e90000 {
1874 compatible = "fsl,imx8mp-lcdif";
1880 clock-names = "pix", "axi", "disp_axi";
1881 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;
1886 remote-endpoint = <&ldb_from_lcdif2>;
1891 media_blk_ctrl: blk-ctrl@32ec0000 {
1892 compatible = "fsl,imx8mp-media-blk-ctrl",
1895 #address-cells = <1>;
1896 #size-cells = <1>;
1897 power-domains = <&pgc_mediamix>,
1907 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1908 "lcdif1", "isi", "mipi-csi2",
1910 "mipi-dsi2";
1920 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
1931 clock-names = "apb", "axi", "cam1", "cam2",
1940 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1946 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1951 assigned-clock-rates = <500000000>, <200000000>,
1954 #power-domain-cells = <1>;
1957 compatible = "fsl,imx8mp-ldb";
1959 reg-names = "ldb", "lvds";
1961 clock-names = "ldb";
1962 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
1963 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
1967 #address-cells = <1>;
1968 #size-cells = <0>;
1974 remote-endpoint = <&lcdif2_to_ldb>;
1995 pcie_phy: pcie-phy@32f00000 {
1996 compatible = "fsl,imx8mp-pcie-phy";
2000 reset-names = "pciephy", "perst";
2001 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
2002 #phy-cells = <0>;
2006 hsio_blk_ctrl: blk-ctrl@32f10000 {
2007 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
2011 clock-names = "usb", "pcie";
2012 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
2015 power-domain-names = "bus", "usb", "usb-phy1",
2016 "usb-phy2", "pcie", "pcie-phy";
2021 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
2022 #power-domain-cells = <1>;
2023 #clock-cells = <0>;
2026 hdmi_blk_ctrl: blk-ctrl@32fc0000 {
2027 compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
2034 clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc";
2035 power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>,
2040 power-domain-names = "bus", "irqsteer", "lcdif",
2042 "hdmi-tx", "hdmi-tx-phy",
2044 #power-domain-cells = <1>;
2047 irqsteer_hdmi: interrupt-controller@32fc2000 {
2048 compatible = "fsl,imx8mp-irqsteer", "fsl,imx-irqsteer";
2051 interrupt-controller;
2052 #interrupt-cells = <1>;
2054 fsl,num-irqs = <64>;
2056 clock-names = "ipg";
2057 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>;
2060 hdmi_pvi: display-bridge@32fc4000 {
2061 compatible = "fsl,imx8mp-hdmi-pvi";
2063 interrupt-parent = <&irqsteer_hdmi>;
2065 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
2069 #address-cells = <1>;
2070 #size-cells = <0>;
2075 remote-endpoint = <&lcdif3_to_pvi>;
2082 remote-endpoint = <&hdmi_tx_from_pvi>;
2088 lcdif3: display-controller@32fc6000 {
2089 compatible = "fsl,imx8mp-lcdif";
2091 interrupt-parent = <&irqsteer_hdmi>;
2096 clock-names = "pix", "axi", "disp_axi";
2097 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>;
2102 remote-endpoint = <&pvi_from_lcdif3>;
2108 compatible = "fsl,imx8mp-hdmi-tx";
2110 interrupt-parent = <&irqsteer_hdmi>;
2116 clock-names = "iahb", "isfr", "cec", "pix";
2117 assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>;
2118 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
2119 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
2120 reg-io-width = <1>;
2124 #address-cells = <1>;
2125 #size-cells = <0>;
2131 remote-endpoint = <&pvi_to_hdmi_tx>;
2143 compatible = "fsl,imx8mp-hdmi-phy";
2147 clock-names = "apb", "ref";
2148 assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>;
2149 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2150 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
2151 #clock-cells = <0>;
2152 #phy-cells = <0>;
2158 compatible = "fsl,imx8mp-pcie";
2160 reg-names = "dbi", "config";
2164 clock-names = "pcie", "pcie_bus", "pcie_aux";
2165 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
2166 assigned-clock-rates = <10000000>;
2167 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
2168 #address-cells = <3>;
2169 #size-cells = <2>;
2171 bus-range = <0x00 0xff>;
2173 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
2174 num-lanes = <1>;
2175 num-viewport = <4>;
2177 interrupt-names = "msi";
2178 #interrupt-cells = <1>;
2179 interrupt-map-mask = <0 0 0 0x7>;
2180 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
2184 fsl,max-link-speed = <3>;
2185 linux,pci-domain = <0>;
2186 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
2189 reset-names = "apps", "turnoff";
2191 phy-names = "pcie-phy";
2195 pcie_ep: pcie-ep@33800000 {
2196 compatible = "fsl,imx8mp-pcie-ep";
2201 reg-names = "dbi", "addr_space", "dbi2", "atu";
2205 clock-names = "pcie", "pcie_bus", "pcie_aux";
2206 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
2207 assigned-clock-rates = <10000000>;
2208 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
2209 num-lanes = <1>;
2211 interrupt-names = "dma";
2212 fsl,max-link-speed = <3>;
2213 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
2216 reset-names = "apps", "turnoff";
2218 phy-names = "pcie-phy";
2219 num-ib-windows = <4>;
2220 num-ob-windows = <4>;
2232 clock-names = "core", "shader", "bus", "reg";
2233 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
2235 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
2237 assigned-clock-rates = <800000000>, <800000000>;
2238 power-domains = <&pgc_gpu3d>;
2248 clock-names = "core", "bus", "reg";
2249 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
2250 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
2251 assigned-clock-rates = <800000000>;
2252 power-domains = <&pgc_gpu2d>;
2255 vpu_g1: video-codec@38300000 {
2256 compatible = "nxp,imx8mm-vpu-g1";
2260 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
2261 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
2262 assigned-clock-rates = <600000000>;
2263 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;
2266 vpu_g2: video-codec@38310000 {
2267 compatible = "nxp,imx8mq-vpu-g2";
2271 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;
2272 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
2273 assigned-clock-rates = <500000000>;
2274 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;
2277 vpumix_blk_ctrl: blk-ctrl@38330000 {
2278 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
2280 #power-domain-cells = <1>;
2281 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
2283 power-domain-names = "bus", "g1", "g2", "vc8000e";
2287 clock-names = "g1", "g2", "vc8000e";
2288 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;
2289 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
2290 assigned-clock-rates = <600000000>, <600000000>;
2294 interconnect-names = "g1", "g2", "vc8000e";
2305 clock-names = "core", "shader", "bus", "reg";
2306 power-domains = <&pgc_mlmix>;
2309 gic: interrupt-controller@38800000 {
2310 compatible = "arm,gic-v3";
2313 #interrupt-cells = <3>;
2314 interrupt-controller;
2316 interrupt-parent = <&gic>;
2319 edacmc: memory-controller@3d400000 {
2320 compatible = "snps,ddrc-3.80a";
2325 ddr-pmu@3d800000 {
2326 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
2331 usb3_phy0: usb-phy@381f0040 {
2332 compatible = "fsl,imx8mp-usb-phy";
2335 clock-names = "phy";
2336 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2337 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2338 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
2339 #phy-cells = <0>;
2344 compatible = "fsl,imx8mp-dwc3";
2349 clock-names = "hsio", "suspend";
2351 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2352 #address-cells = <1>;
2353 #size-cells = <1>;
2354 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2364 clock-names = "bus_early", "ref", "suspend";
2367 phy-names = "usb2-phy", "usb3-phy";
2368 snps,gfladj-refclk-lpm-sel-quirk;
2369 snps,parkmode-disable-ss-quirk;
2374 usb3_phy1: usb-phy@382f0040 {
2375 compatible = "fsl,imx8mp-usb-phy";
2378 clock-names = "phy";
2379 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2380 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2381 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
2382 #phy-cells = <0>;
2387 compatible = "fsl,imx8mp-dwc3";
2392 clock-names = "hsio", "suspend";
2394 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2395 #address-cells = <1>;
2396 #size-cells = <1>;
2397 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2407 clock-names = "bus_early", "ref", "suspend";
2410 phy-names = "usb2-phy", "usb3-phy";
2411 snps,gfladj-refclk-lpm-sel-quirk;
2412 snps,parkmode-disable-ss-quirk;
2417 compatible = "fsl,imx8mp-dsp";
2419 mbox-names = "txdb0", "txdb1",
2423 memory-region = <&dsp_reserved>;