Lines Matching +full:0 +full:x30360000
48 #size-cells = <0>;
50 A53_0: cpu@0 {
53 reg = <0x0>;
57 i-cache-size = <0x8000>;
60 d-cache-size = <0x8000>;
73 reg = <0x1>;
77 i-cache-size = <0x8000>;
80 d-cache-size = <0x8000>;
91 reg = <0x2>;
95 i-cache-size = <0x8000>;
98 d-cache-size = <0x8000>;
109 reg = <0x3>;
113 i-cache-size = <0x8000>;
116 d-cache-size = <0x8000>;
128 cache-size = <0x80000>;
141 opp-supported-hw = <0x8a0>, <0x7>;
149 opp-supported-hw = <0xa0>, <0x7>;
157 opp-supported-hw = <0x20>, <0x3>;
165 #clock-cells = <0>;
172 #clock-cells = <0>;
179 #clock-cells = <0>;
186 #clock-cells = <0>;
193 #clock-cells = <0>;
200 #clock-cells = <0>;
214 #size-cells = <0>;
216 port@0 {
217 reg = <0>;
265 reg = <0 0x92400000 0 0x2000000>;
286 thermal-sensors = <&tmu 0>;
354 soc: soc@0 {
358 ranges = <0x0 0x0 0x0 0x3e000000>;
364 reg = <0x28440000 0x1000>;
380 reg = <0x28540000 0x1000>;
396 reg = <0x28640000 0x1000>;
412 reg = <0x28740000 0x1000>;
428 reg = <0x28c03000 0x1000>;
434 #size-cells = <0>;
436 port@0 {
437 reg = <0>;
473 reg = <0x28c04000 0x1000>;
496 reg = <0x28c06000 0x1000>;
511 reg = <0x30000000 0x400000>;
518 reg = <0x30200000 0x10000>;
526 gpio-ranges = <&iomuxc 0 5 30>;
531 reg = <0x30210000 0x10000>;
539 gpio-ranges = <&iomuxc 0 35 21>;
544 reg = <0x30220000 0x10000>;
552 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
557 reg = <0x30230000 0x10000>;
565 gpio-ranges = <&iomuxc 0 82 32>;
570 reg = <0x30240000 0x10000>;
578 gpio-ranges = <&iomuxc 0 114 30>;
583 reg = <0x30260000 0x10000>;
592 reg = <0x30280000 0x10000>;
600 reg = <0x30290000 0x10000>;
608 reg = <0x302a0000 0x10000>;
616 reg = <0x302d0000 0x10000>;
624 reg = <0x302e0000 0x10000>;
632 reg = <0x302f0000 0x10000>;
640 reg = <0x30330000 0x10000>;
645 reg = <0x30340000 0x10000>;
650 reg = <0x30350000 0x10000>;
662 * Fuse Address = (ADDR * 4) + 0x400
665 * +0x10 in Fusemap Description Table (e.g.
666 * reg = <0x8 0x8> describes fuses 0x420 and
667 * 0x430).
669 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
670 reg = <0x8 0x8>;
673 cpu_speed_grade: speed-grade@10 { /* 0x440 */
674 reg = <0x10 4>;
677 eth_mac1: mac-address@90 { /* 0x640 */
678 reg = <0x90 6>;
681 eth_mac2: mac-address@96 { /* 0x658 */
682 reg = <0x96 6>;
685 tmu_calib: calib@264 { /* 0xd90-0xdc0 */
686 reg = <0x264 0x10>;
692 reg = <0x30360000 0x10000>;
697 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
698 reg = <0x30370000 0x10000>;
701 compatible = "fsl,sec-v4.0-mon-rtc-lp";
703 offset = <0x34>;
711 compatible = "fsl,sec-v4.0-pwrkey";
729 reg = <0x30380000 0x10000>;
747 assigned-clock-rates = <0>, <0>,
755 reg = <0x30390000 0x10000>;
762 reg = <0x303a0000 0x1000>;
770 #size-cells = <0>;
772 pgc_mipi_phy1: power-domain@0 {
773 #power-domain-cells = <0>;
778 #power-domain-cells = <0>;
783 #power-domain-cells = <0>;
788 #power-domain-cells = <0>;
793 #power-domain-cells = <0>;
810 #power-domain-cells = <0>;
823 #power-domain-cells = <0>;
830 #power-domain-cells = <0>;
842 #power-domain-cells = <0>;
848 #power-domain-cells = <0>;
856 #power-domain-cells = <0>;
863 #power-domain-cells = <0>;
870 #power-domain-cells = <0>;
878 #power-domain-cells = <0>;
885 #power-domain-cells = <0>;
897 #power-domain-cells = <0>;
902 #power-domain-cells = <0>;
907 #power-domain-cells = <0>;
917 #power-domain-cells = <0>;
927 reg = <0x30400000 0x400000>;
934 reg = <0x30660000 0x10000>;
945 reg = <0x30670000 0x10000>;
956 reg = <0x30680000 0x10000>;
967 reg = <0x30690000 0x10000>;
978 reg = <0x306a0000 0x20000>;
986 reg = <0x306e0000 0x10000>;
994 reg = <0x306f0000 0x10000>;
1002 reg = <0x30700000 0x10000>;
1011 reg = <0x30800000 0x400000>;
1018 reg = <0x30800000 0x100000>;
1025 #size-cells = <0>;
1027 reg = <0x30820000 0x10000>;
1035 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1042 #size-cells = <0>;
1044 reg = <0x30830000 0x10000>;
1059 #size-cells = <0>;
1061 reg = <0x30840000 0x10000>;
1076 reg = <0x30860000 0x10000>;
1081 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
1088 reg = <0x30880000 0x10000>;
1093 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
1100 reg = <0x30890000 0x10000>;
1105 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
1112 reg = <0x308c0000 0x10000>;
1120 fsl,clk-source = /bits/ 8 <0>;
1121 fsl,stop-mode = <&gpr 0x10 4>;
1127 reg = <0x308d0000 0x10000>;
1135 fsl,clk-source = /bits/ 8 <0>;
1136 fsl,stop-mode = <&gpr 0x10 5>;
1142 compatible = "fsl,sec-v4.0";
1145 reg = <0x30900000 0x40000>;
1146 ranges = <0 0x30900000 0x40000>;
1153 compatible = "fsl,sec-v4.0-job-ring";
1154 reg = <0x1000 0x1000>;
1160 compatible = "fsl,sec-v4.0-job-ring";
1161 reg = <0x2000 0x1000>;
1166 compatible = "fsl,sec-v4.0-job-ring";
1167 reg = <0x3000 0x1000>;
1175 #size-cells = <0>;
1176 reg = <0x30a20000 0x10000>;
1185 #size-cells = <0>;
1186 reg = <0x30a30000 0x10000>;
1195 #size-cells = <0>;
1196 reg = <0x30a40000 0x10000>;
1205 #size-cells = <0>;
1206 reg = <0x30a50000 0x10000>;
1214 reg = <0x30a60000 0x10000>;
1219 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1226 reg = <0x30aa0000 0x10000>;
1234 reg = <0x30e60000 0x10000>;
1243 #size-cells = <0>;
1244 reg = <0x30ad0000 0x10000>;
1253 #size-cells = <0>;
1254 reg = <0x30ae0000 0x10000>;
1262 reg = <0x30b40000 0x10000>;
1276 reg = <0x30b50000 0x10000>;
1290 reg = <0x30b60000 0x10000>;
1304 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1313 #size-cells = <0>;
1319 reg = <0x30bd0000 0x10000>;
1330 reg = <0x30be0000 0x10000>;
1350 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1355 fsl,stop-mode = <&gpr 0x10 3>;
1361 reg = <0x30bf0000 0x10000>;
1376 assigned-clock-rates = <0>, <100000000>, <125000000>;
1379 intf_mode = <&gpr 0x4>;
1386 reg = <0x30c00000 0x400000>;
1393 reg = <0x30c00000 0x100000>;
1400 reg = <0x30c10000 0x10000>;
1401 #sound-dai-cells = <0>;
1408 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
1416 reg = <0x30c20000 0x10000>;
1417 #sound-dai-cells = <0>;
1424 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
1432 reg = <0x30c30000 0x10000>;
1433 #sound-dai-cells = <0>;
1440 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
1448 reg = <0x30c50000 0x10000>;
1449 #sound-dai-cells = <0>;
1456 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
1464 reg = <0x30c60000 0x10000>;
1465 #sound-dai-cells = <0>;
1472 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
1480 reg = <0x30c80000 0x10000>;
1481 #sound-dai-cells = <0>;
1488 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
1496 reg = <0x30c90000 0x10000>;
1500 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
1501 <&sdma2 18 23 0> , <&sdma2 19 23 0>,
1502 <&sdma2 20 23 0> , <&sdma2 21 23 0>,
1503 <&sdma2 22 23 0> , <&sdma2 23 23 0>;
1516 reg = <0x30ca0000 0x10000>;
1517 #sound-dai-cells = <0>;
1529 dmas = <&sdma2 24 25 0x80000000>;
1536 reg = <0x30cb0000 0x10000>;
1540 dmas = <&sdma2 26 2 0>;
1547 reg = <0x30cc0000 0x800>,
1548 <0x30cc0800 0x400>,
1549 <0x30cc0c00 0x080>,
1550 <0x30cc0e00 0x080>;
1553 interrupts = /* XCVR IRQ 0 */
1564 dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
1566 resets = <&audio_blk_ctrl 0>;
1573 reg = <0x30e00000 0x10000>;
1584 reg = <0x30e10000 0x10000>;
1595 reg = <0x30e20000 0x10000>;
1617 reg = <0x32700000 0x100000>;
1637 reg = <0x32c00000 0x400000>;
1644 reg = <0x32e00000 0x4000>;
1656 #size-cells = <0>;
1658 port@0 {
1659 reg = <0>;
1678 reg = <0x32e10000 0x10000>;
1685 fsl,blk-ctrl = <&media_blk_ctrl 0>;
1690 #size-cells = <0>;
1700 reg = <0x32e20000 0x10000>;
1712 #size-cells = <0>;
1722 reg = <0x32e30000 0x10000>;
1732 reg = <0x32e40000 0x10000>;
1749 #size-cells = <0>;
1751 port@0 {
1752 reg = <0>;
1767 reg = <0x32e50000 0x10000>;
1784 #size-cells = <0>;
1786 port@0 {
1787 reg = <0>;
1802 reg = <0x32e60000 0x400>;
1818 #size-cells = <0>;
1820 port@0 {
1821 reg = <0>;
1839 reg = <0x32e80000 0x10000>;
1857 reg = <0x32e90000 0x10000>;
1876 reg = <0x32ec0000 0x10000>;
1934 <0>, <0>, <500000000>,
1940 reg = <0x5c 0x4>, <0x128 0x4>;
1950 #size-cells = <0>;
1952 port@0 {
1953 reg = <0>;
1979 reg = <0x32f00000 0x10000>;
1984 #phy-cells = <0>;
1990 reg = <0x32f10000 0x24>;
2005 #clock-cells = <0>;
2010 reg = <0x32fc0000 0x1000>;
2031 reg = <0x32fc2000 0x1000>;
2044 reg = <0x32fc4000 0x1000>;
2052 #size-cells = <0>;
2054 port@0 {
2055 reg = <0>;
2072 reg = <0x32fc6000 0x1000>;
2091 reg = <0x32fd8000 0x7eff>;
2093 interrupts = <0>;
2107 #size-cells = <0>;
2109 port@0 {
2110 reg = <0>;
2126 reg = <0x32fdff00 0x100>;
2133 #clock-cells = <0>;
2134 #phy-cells = <0>;
2141 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
2153 bus-range = <0x00 0xff>;
2154 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
2155 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
2161 interrupt-map-mask = <0 0 0 0x7>;
2162 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
2163 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2164 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
2165 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
2167 linux,pci-domain = <0>;
2179 reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
2205 reg = <0x38000000 0x8000>;
2222 reg = <0x38008000 0x8000>;
2236 reg = <0x38300000 0x10000>;
2247 reg = <0x38310000 0x10000>;
2258 reg = <0x38330000 0x100>;
2278 reg = <0x38500000 0x200000>;
2290 reg = <0x38800000 0x10000>,
2291 <0x38880000 0xc0000>;
2300 reg = <0x3d400000 0x400000>;
2306 reg = <0x3d800000 0x400000>;
2312 reg = <0x381f0040 0x40>;
2318 #phy-cells = <0>;
2324 reg = <0x32f10100 0x8>,
2325 <0x381f0000 0x20>;
2333 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2339 reg = <0x38100000 0x10000>;
2355 reg = <0x382f0040 0x40>;
2361 #phy-cells = <0>;
2367 reg = <0x32f10108 0x8>,
2368 <0x382f0000 0x20>;
2376 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2382 reg = <0x38200000 0x10000>;
2397 reg = <0x3b6e8000 0x88000>;
2400 mboxes = <&mu2 2 0>, <&mu2 2 1>,
2401 <&mu2 3 0>, <&mu2 3 1>;