Lines Matching +full:0 +full:x30340000
48 #size-cells = <0>;
55 arm,psci-suspend-param = <0x0010033>;
64 A53_0: cpu@0 {
67 reg = <0x0>;
71 i-cache-size = <0x8000>;
74 d-cache-size = <0x8000>;
88 reg = <0x1>;
92 i-cache-size = <0x8000>;
95 d-cache-size = <0x8000>;
107 reg = <0x2>;
111 i-cache-size = <0x8000>;
114 d-cache-size = <0x8000>;
126 reg = <0x3>;
130 i-cache-size = <0x8000>;
133 d-cache-size = <0x8000>;
146 cache-size = <0x80000>;
159 opp-supported-hw = <0x8a0>, <0x7>;
167 opp-supported-hw = <0xa0>, <0x7>;
175 opp-supported-hw = <0x20>, <0x3>;
183 #clock-cells = <0>;
190 #clock-cells = <0>;
197 #clock-cells = <0>;
204 #clock-cells = <0>;
211 #clock-cells = <0>;
218 #clock-cells = <0>;
232 #size-cells = <0>;
234 port@0 {
235 reg = <0>;
283 reg = <0 0x92400000 0 0x2000000>;
304 thermal-sensors = <&tmu 0>;
372 soc: soc@0 {
376 ranges = <0x0 0x0 0x0 0x3e000000>;
382 reg = <0x28440000 0x1000>;
398 reg = <0x28540000 0x1000>;
414 reg = <0x28640000 0x1000>;
430 reg = <0x28740000 0x1000>;
446 reg = <0x28c03000 0x1000>;
452 #size-cells = <0>;
454 port@0 {
455 reg = <0>;
491 reg = <0x28c04000 0x1000>;
514 reg = <0x28c06000 0x1000>;
529 reg = <0x30000000 0x400000>;
536 reg = <0x30200000 0x10000>;
544 gpio-ranges = <&iomuxc 0 5 30>;
549 reg = <0x30210000 0x10000>;
557 gpio-ranges = <&iomuxc 0 35 21>;
562 reg = <0x30220000 0x10000>;
570 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
575 reg = <0x30230000 0x10000>;
583 gpio-ranges = <&iomuxc 0 82 32>;
588 reg = <0x30240000 0x10000>;
596 gpio-ranges = <&iomuxc 0 114 30>;
601 reg = <0x30260000 0x10000>;
610 reg = <0x30280000 0x10000>;
618 reg = <0x30290000 0x10000>;
626 reg = <0x302a0000 0x10000>;
634 reg = <0x302d0000 0x10000>;
642 reg = <0x302e0000 0x10000>;
650 reg = <0x302f0000 0x10000>;
658 reg = <0x30330000 0x10000>;
663 reg = <0x30340000 0x10000>;
668 reg = <0x30350000 0x10000>;
680 * Fuse Address = (ADDR * 4) + 0x400
683 * +0x10 in Fusemap Description Table (e.g.
684 * reg = <0x8 0x8> describes fuses 0x420 and
685 * 0x430).
687 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
688 reg = <0x8 0x8>;
691 cpu_speed_grade: speed-grade@10 { /* 0x440 */
692 reg = <0x10 4>;
695 eth_mac1: mac-address@90 { /* 0x640 */
696 reg = <0x90 6>;
699 eth_mac2: mac-address@96 { /* 0x658 */
700 reg = <0x96 6>;
703 tmu_calib: calib@264 { /* 0xd90-0xdc0 */
704 reg = <0x264 0x10>;
710 reg = <0x30360000 0x10000>;
715 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
716 reg = <0x30370000 0x10000>;
719 compatible = "fsl,sec-v4.0-mon-rtc-lp";
721 offset = <0x34>;
729 compatible = "fsl,sec-v4.0-pwrkey";
747 reg = <0x30380000 0x10000>;
765 assigned-clock-rates = <0>, <0>,
773 reg = <0x30390000 0x10000>;
780 reg = <0x303a0000 0x1000>;
788 #size-cells = <0>;
790 pgc_mipi_phy1: power-domain@0 {
791 #power-domain-cells = <0>;
796 #power-domain-cells = <0>;
801 #power-domain-cells = <0>;
806 #power-domain-cells = <0>;
811 #power-domain-cells = <0>;
828 #power-domain-cells = <0>;
841 #power-domain-cells = <0>;
848 #power-domain-cells = <0>;
860 #power-domain-cells = <0>;
866 #power-domain-cells = <0>;
874 #power-domain-cells = <0>;
881 #power-domain-cells = <0>;
888 #power-domain-cells = <0>;
896 #power-domain-cells = <0>;
903 #power-domain-cells = <0>;
915 #power-domain-cells = <0>;
920 #power-domain-cells = <0>;
925 #power-domain-cells = <0>;
935 #power-domain-cells = <0>;
945 reg = <0x30400000 0x400000>;
952 reg = <0x30660000 0x10000>;
963 reg = <0x30670000 0x10000>;
974 reg = <0x30680000 0x10000>;
985 reg = <0x30690000 0x10000>;
996 reg = <0x306a0000 0x20000>;
1004 reg = <0x306e0000 0x10000>;
1012 reg = <0x306f0000 0x10000>;
1020 reg = <0x30700000 0x10000>;
1029 reg = <0x30800000 0x400000>;
1036 reg = <0x30800000 0x100000>;
1043 #size-cells = <0>;
1045 reg = <0x30820000 0x10000>;
1053 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1060 #size-cells = <0>;
1062 reg = <0x30830000 0x10000>;
1077 #size-cells = <0>;
1079 reg = <0x30840000 0x10000>;
1094 reg = <0x30860000 0x10000>;
1099 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
1106 reg = <0x30880000 0x10000>;
1111 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
1118 reg = <0x30890000 0x10000>;
1123 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
1130 reg = <0x308c0000 0x10000>;
1138 fsl,clk-source = /bits/ 8 <0>;
1139 fsl,stop-mode = <&gpr 0x10 4>;
1145 reg = <0x308d0000 0x10000>;
1153 fsl,clk-source = /bits/ 8 <0>;
1154 fsl,stop-mode = <&gpr 0x10 5>;
1160 compatible = "fsl,sec-v4.0";
1163 reg = <0x30900000 0x40000>;
1164 ranges = <0 0x30900000 0x40000>;
1171 compatible = "fsl,sec-v4.0-job-ring";
1172 reg = <0x1000 0x1000>;
1178 compatible = "fsl,sec-v4.0-job-ring";
1179 reg = <0x2000 0x1000>;
1184 compatible = "fsl,sec-v4.0-job-ring";
1185 reg = <0x3000 0x1000>;
1193 #size-cells = <0>;
1194 reg = <0x30a20000 0x10000>;
1203 #size-cells = <0>;
1204 reg = <0x30a30000 0x10000>;
1213 #size-cells = <0>;
1214 reg = <0x30a40000 0x10000>;
1223 #size-cells = <0>;
1224 reg = <0x30a50000 0x10000>;
1232 reg = <0x30a60000 0x10000>;
1237 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1244 reg = <0x30aa0000 0x10000>;
1252 reg = <0x30e60000 0x10000>;
1261 #size-cells = <0>;
1262 reg = <0x30ad0000 0x10000>;
1271 #size-cells = <0>;
1272 reg = <0x30ae0000 0x10000>;
1280 reg = <0x30b40000 0x10000>;
1294 reg = <0x30b50000 0x10000>;
1308 reg = <0x30b60000 0x10000>;
1322 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1331 #size-cells = <0>;
1337 reg = <0x30bd0000 0x10000>;
1348 reg = <0x30be0000 0x10000>;
1368 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1373 fsl,stop-mode = <&gpr 0x10 3>;
1379 reg = <0x30bf0000 0x10000>;
1394 assigned-clock-rates = <0>, <100000000>, <125000000>;
1397 intf_mode = <&gpr 0x4>;
1404 reg = <0x30c00000 0x400000>;
1411 reg = <0x30c00000 0x100000>;
1418 reg = <0x30c10000 0x10000>;
1419 #sound-dai-cells = <0>;
1426 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
1434 reg = <0x30c20000 0x10000>;
1435 #sound-dai-cells = <0>;
1442 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
1450 reg = <0x30c30000 0x10000>;
1451 #sound-dai-cells = <0>;
1458 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
1466 reg = <0x30c50000 0x10000>;
1467 #sound-dai-cells = <0>;
1474 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
1482 reg = <0x30c60000 0x10000>;
1483 #sound-dai-cells = <0>;
1490 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
1498 reg = <0x30c80000 0x10000>;
1499 #sound-dai-cells = <0>;
1506 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
1514 reg = <0x30c90000 0x10000>;
1518 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
1519 <&sdma2 18 23 0> , <&sdma2 19 23 0>,
1520 <&sdma2 20 23 0> , <&sdma2 21 23 0>,
1521 <&sdma2 22 23 0> , <&sdma2 23 23 0>;
1534 reg = <0x30ca0000 0x10000>;
1535 #sound-dai-cells = <0>;
1547 dmas = <&sdma2 24 25 0x80000000>;
1554 reg = <0x30cb0000 0x10000>;
1558 dmas = <&sdma2 26 2 0>;
1565 reg = <0x30cc0000 0x800>,
1566 <0x30cc0800 0x400>,
1567 <0x30cc0c00 0x080>,
1568 <0x30cc0e00 0x080>;
1571 interrupts = /* XCVR IRQ 0 */
1582 dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
1584 resets = <&audio_blk_ctrl 0>;
1591 reg = <0x30e00000 0x10000>;
1602 reg = <0x30e10000 0x10000>;
1613 reg = <0x30e20000 0x10000>;
1635 reg = <0x32700000 0x100000>;
1655 reg = <0x32c00000 0x400000>;
1662 reg = <0x32e00000 0x4000>;
1674 #size-cells = <0>;
1676 port@0 {
1677 reg = <0>;
1696 reg = <0x32e10000 0x10000>;
1703 fsl,blk-ctrl = <&media_blk_ctrl 0>;
1708 #size-cells = <0>;
1718 reg = <0x32e20000 0x10000>;
1730 #size-cells = <0>;
1740 reg = <0x32e30000 0x10000>;
1750 reg = <0x32e40000 0x10000>;
1767 #size-cells = <0>;
1769 port@0 {
1770 reg = <0>;
1785 reg = <0x32e50000 0x10000>;
1802 #size-cells = <0>;
1804 port@0 {
1805 reg = <0>;
1820 reg = <0x32e60000 0x400>;
1836 #size-cells = <0>;
1838 port@0 {
1839 reg = <0>;
1857 reg = <0x32e80000 0x10000>;
1875 reg = <0x32e90000 0x10000>;
1894 reg = <0x32ec0000 0x10000>;
1952 <0>, <0>, <500000000>,
1958 reg = <0x5c 0x4>, <0x128 0x4>;
1968 #size-cells = <0>;
1970 port@0 {
1971 reg = <0>;
1997 reg = <0x32f00000 0x10000>;
2002 #phy-cells = <0>;
2008 reg = <0x32f10000 0x24>;
2023 #clock-cells = <0>;
2028 reg = <0x32fc0000 0x1000>;
2049 reg = <0x32fc2000 0x1000>;
2062 reg = <0x32fc4000 0x1000>;
2070 #size-cells = <0>;
2072 port@0 {
2073 reg = <0>;
2090 reg = <0x32fc6000 0x1000>;
2109 reg = <0x32fd8000 0x7eff>;
2111 interrupts = <0>;
2125 #size-cells = <0>;
2127 port@0 {
2128 reg = <0>;
2144 reg = <0x32fdff00 0x100>;
2151 #clock-cells = <0>;
2152 #phy-cells = <0>;
2159 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
2171 bus-range = <0x00 0xff>;
2172 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
2173 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
2179 interrupt-map-mask = <0 0 0 0x7>;
2180 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
2181 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2182 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
2183 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
2185 linux,pci-domain = <0>;
2197 reg = <0x33800000 0x100000>,
2198 <0x18000000 0x8000000>,
2199 <0x33900000 0x100000>,
2200 <0x33b00000 0x100000>;
2226 reg = <0x38000000 0x8000>;
2243 reg = <0x38008000 0x8000>;
2257 reg = <0x38300000 0x10000>;
2268 reg = <0x38310000 0x10000>;
2279 reg = <0x38330000 0x100>;
2299 reg = <0x38500000 0x200000>;
2311 reg = <0x38800000 0x10000>,
2312 <0x38880000 0xc0000>;
2321 reg = <0x3d400000 0x400000>;
2327 reg = <0x3d800000 0x400000>;
2333 reg = <0x381f0040 0x40>;
2339 #phy-cells = <0>;
2345 reg = <0x32f10100 0x8>,
2346 <0x381f0000 0x20>;
2354 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2360 reg = <0x38100000 0x10000>;
2376 reg = <0x382f0040 0x40>;
2382 #phy-cells = <0>;
2388 reg = <0x32f10108 0x8>,
2389 <0x382f0000 0x20>;
2397 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2403 reg = <0x38200000 0x10000>;
2418 reg = <0x3b6e8000 0x88000>;
2421 mboxes = <&mu2 2 0>, <&mu2 2 1>,
2422 <&mu2 3 0>, <&mu2 3 1>;