Lines Matching +full:imx28 +full:- +full:i2c
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/power/imx8mn-power.h>
8 #include <dt-bindings/reset/imx8mq-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mn-pinfunc.h"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
45 #address-cells = <1>;
46 #size-cells = <0>;
48 idle-states {
49 entry-method = "psci";
51 cpu_pd_wait: cpu-pd-wait {
52 compatible = "arm,idle-state";
53 arm,psci-suspend-param = <0x0010033>;
54 local-timer-stop;
55 entry-latency-us = <1000>;
56 exit-latency-us = <700>;
57 min-residency-us = <2700>;
63 compatible = "arm,cortex-a53";
66 enable-method = "psci";
67 i-cache-size = <0x8000>;
68 i-cache-line-size = <64>;
69 i-cache-sets = <256>;
70 d-cache-size = <0x8000>;
71 d-cache-line-size = <64>;
72 d-cache-sets = <128>;
73 next-level-cache = <&A53_L2>;
74 operating-points-v2 = <&a53_opp_table>;
75 nvmem-cells = <&cpu_speed_grade>;
76 nvmem-cell-names = "speed_grade";
77 cpu-idle-states = <&cpu_pd_wait>;
78 #cooling-cells = <2>;
83 compatible = "arm,cortex-a53";
86 enable-method = "psci";
87 i-cache-size = <0x8000>;
88 i-cache-line-size = <64>;
89 i-cache-sets = <256>;
90 d-cache-size = <0x8000>;
91 d-cache-line-size = <64>;
92 d-cache-sets = <128>;
93 next-level-cache = <&A53_L2>;
94 operating-points-v2 = <&a53_opp_table>;
95 cpu-idle-states = <&cpu_pd_wait>;
96 #cooling-cells = <2>;
101 compatible = "arm,cortex-a53";
104 enable-method = "psci";
105 i-cache-size = <0x8000>;
106 i-cache-line-size = <64>;
107 i-cache-sets = <256>;
108 d-cache-size = <0x8000>;
109 d-cache-line-size = <64>;
110 d-cache-sets = <128>;
111 next-level-cache = <&A53_L2>;
112 operating-points-v2 = <&a53_opp_table>;
113 cpu-idle-states = <&cpu_pd_wait>;
114 #cooling-cells = <2>;
119 compatible = "arm,cortex-a53";
122 enable-method = "psci";
123 i-cache-size = <0x8000>;
124 i-cache-line-size = <64>;
125 i-cache-sets = <256>;
126 d-cache-size = <0x8000>;
127 d-cache-line-size = <64>;
128 d-cache-sets = <128>;
129 next-level-cache = <&A53_L2>;
130 operating-points-v2 = <&a53_opp_table>;
131 cpu-idle-states = <&cpu_pd_wait>;
132 #cooling-cells = <2>;
135 A53_L2: l2-cache0 {
137 cache-level = <2>;
138 cache-unified;
139 cache-size = <0x80000>;
140 cache-line-size = <64>;
141 cache-sets = <512>;
145 a53_opp_table: opp-table {
146 compatible = "operating-points-v2";
147 opp-shared;
149 opp-1200000000 {
150 opp-hz = /bits/ 64 <1200000000>;
151 opp-microvolt = <850000>;
152 opp-supported-hw = <0xb00>, <0x7>;
153 clock-latency-ns = <150000>;
154 opp-suspend;
157 opp-1400000000 {
158 opp-hz = /bits/ 64 <1400000000>;
159 opp-microvolt = <950000>;
160 opp-supported-hw = <0x300>, <0x7>;
161 clock-latency-ns = <150000>;
162 opp-suspend;
165 opp-1500000000 {
166 opp-hz = /bits/ 64 <1500000000>;
167 opp-microvolt = <1000000>;
168 opp-supported-hw = <0x100>, <0x3>;
169 clock-latency-ns = <150000>;
170 opp-suspend;
174 osc_32k: clock-osc-32k {
175 compatible = "fixed-clock";
176 #clock-cells = <0>;
177 clock-frequency = <32768>;
178 clock-output-names = "osc_32k";
181 osc_24m: clock-osc-24m {
182 compatible = "fixed-clock";
183 #clock-cells = <0>;
184 clock-frequency = <24000000>;
185 clock-output-names = "osc_24m";
188 clk_ext1: clock-ext1 {
189 compatible = "fixed-clock";
190 #clock-cells = <0>;
191 clock-frequency = <133000000>;
192 clock-output-names = "clk_ext1";
195 clk_ext2: clock-ext2 {
196 compatible = "fixed-clock";
197 #clock-cells = <0>;
198 clock-frequency = <133000000>;
199 clock-output-names = "clk_ext2";
202 clk_ext3: clock-ext3 {
203 compatible = "fixed-clock";
204 #clock-cells = <0>;
205 clock-frequency = <133000000>;
206 clock-output-names = "clk_ext3";
209 clk_ext4: clock-ext4 {
210 compatible = "fixed-clock";
211 #clock-cells = <0>;
212 clock-frequency = <133000000>;
213 clock-output-names = "clk_ext4";
217 compatible = "arm,cortex-a53-pmu";
223 compatible = "arm,psci-1.0";
227 thermal-zones {
228 cpu-thermal {
229 polling-delay-passive = <250>;
230 polling-delay = <2000>;
231 thermal-sensors = <&tmu>;
246 cooling-maps {
249 cooling-device =
260 compatible = "arm,armv8-timer";
265 clock-frequency = <8000000>;
266 arm,no-tick-in-suspend;
270 compatible = "fsl,imx8mn-soc", "simple-bus";
271 #address-cells = <1>;
272 #size-cells = <1>;
274 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
275 nvmem-cells = <&imx8mn_uid>;
276 nvmem-cell-names = "soc_unique_id";
279 compatible = "fsl,aips-bus", "simple-bus";
281 #address-cells = <1>;
282 #size-cells = <1>;
285 spba2: spba-bus@30000000 {
286 compatible = "fsl,spba-bus", "simple-bus";
287 #address-cells = <1>;
288 #size-cells = <1>;
293 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
295 #sound-dai-cells = <0>;
301 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
303 dma-names = "rx", "tx";
308 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
310 #sound-dai-cells = <0>;
316 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
318 dma-names = "rx", "tx";
323 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
325 #sound-dai-cells = <0>;
331 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
333 dma-names = "rx", "tx";
334 fsl,shared-interrupt;
340 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
342 #sound-dai-cells = <0>;
348 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
350 dma-names = "rx", "tx";
354 micfil: audio-controller@30080000 {
355 compatible = "fsl,imx8mm-micfil";
366 clock-names = "ipg_clk", "ipg_clk_app",
369 dma-names = "rx";
370 #sound-dai-cells = <0>;
375 compatible = "fsl,imx35-spdif";
388 clock-names = "core", "rxtx0",
394 dma-names = "rx", "tx";
399 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
401 #sound-dai-cells = <0>;
407 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
409 dma-names = "rx", "tx";
414 compatible = "fsl,imx8mn-easrc";
418 clock-names = "mem";
423 dma-names = "ctx0_rx", "ctx0_tx",
427 firmware-name = "imx/easrc/easrc-imx8mn.bin";
428 fsl,asrc-rate = <8000>;
429 fsl,asrc-format = <2>;
435 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
440 gpio-controller;
441 #gpio-cells = <2>;
442 interrupt-controller;
443 #interrupt-cells = <2>;
444 gpio-ranges = <&iomuxc 0 10 30>;
448 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
453 gpio-controller;
454 #gpio-cells = <2>;
455 interrupt-controller;
456 #interrupt-cells = <2>;
457 gpio-ranges = <&iomuxc 0 40 21>;
461 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
466 gpio-controller;
467 #gpio-cells = <2>;
468 interrupt-controller;
469 #interrupt-cells = <2>;
470 gpio-ranges = <&iomuxc 0 61 26>;
474 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
479 gpio-controller;
480 #gpio-cells = <2>;
481 interrupt-controller;
482 #interrupt-cells = <2>;
483 gpio-ranges = <&iomuxc 21 108 11>;
487 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
492 gpio-controller;
493 #gpio-cells = <2>;
494 interrupt-controller;
495 #interrupt-cells = <2>;
496 gpio-ranges = <&iomuxc 0 119 30>;
500 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
503 nvmem-cells = <&tmu_calib>;
504 nvmem-cell-names = "calib";
505 #thermal-sensor-cells = <0>;
509 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
517 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
525 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
532 sdma3: dma-controller@302b0000 {
533 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
538 clock-names = "ipg", "ahb";
539 #dma-cells = <3>;
540 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
543 sdma2: dma-controller@302c0000 {
544 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
549 clock-names = "ipg", "ahb";
550 #dma-cells = <3>;
551 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
555 compatible = "fsl,imx8mn-iomuxc";
560 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
565 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
568 #address-cells = <1>;
569 #size-cells = <1>;
584 imx8mn_uid: unique-id@4 { /* 0x410-0x420 */
588 cpu_speed_grade: speed-grade@10 { /* 0x440 */
596 fec_mac_address: mac-address@90 { /* 0x640 */
601 anatop: clock-controller@30360000 {
602 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
604 #clock-cells = <1>;
608 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
611 snvs_rtc: snvs-rtc-lp {
612 compatible = "fsl,sec-v4.0-mon-rtc-lp";
618 clock-names = "snvs-rtc";
621 snvs_pwrkey: snvs-powerkey {
622 compatible = "fsl,sec-v4.0-pwrkey";
626 clock-names = "snvs-pwrkey";
628 wakeup-source;
633 clk: clock-controller@30380000 {
634 compatible = "fsl,imx8mn-ccm";
638 #clock-cells = <1>;
641 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
643 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
651 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
655 assigned-clock-rates = <0>, <0>, <0>,
663 src: reset-controller@30390000 {
664 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
667 #reset-cells = <1>;
671 compatible = "fsl,imx8mn-gpc";
673 interrupt-parent = <&gic>;
677 #address-cells = <1>;
678 #size-cells = <0>;
680 pgc_hsiomix: power-domain@0 {
681 #power-domain-cells = <0>;
686 pgc_otg1: power-domain@1 {
687 #power-domain-cells = <0>;
691 pgc_gpumix: power-domain@2 {
692 #power-domain-cells = <0>;
700 pgc_dispmix: power-domain@3 {
701 #power-domain-cells = <0>;
707 pgc_mipi: power-domain@4 {
708 #power-domain-cells = <0>;
710 power-domains = <&pgc_dispmix>;
717 compatible = "fsl,aips-bus", "simple-bus";
719 #address-cells = <1>;
720 #size-cells = <1>;
724 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
729 clock-names = "ipg", "per";
730 #pwm-cells = <3>;
735 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
740 clock-names = "ipg", "per";
741 #pwm-cells = <3>;
746 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
751 clock-names = "ipg", "per";
752 #pwm-cells = <3>;
757 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
762 clock-names = "ipg", "per";
763 #pwm-cells = <3>;
768 compatible = "nxp,sysctr-timer";
772 clock-names = "per";
777 compatible = "fsl,aips-bus", "simple-bus";
779 #address-cells = <1>;
780 #size-cells = <1>;
783 spba1: spba-bus@30800000 {
784 compatible = "fsl,spba-bus", "simple-bus";
785 #address-cells = <1>;
786 #size-cells = <1>;
791 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
792 #address-cells = <1>;
793 #size-cells = <0>;
798 clock-names = "ipg", "per";
800 dma-names = "rx", "tx";
805 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
806 #address-cells = <1>;
807 #size-cells = <0>;
812 clock-names = "ipg", "per";
814 dma-names = "rx", "tx";
819 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
820 #address-cells = <1>;
821 #size-cells = <0>;
826 clock-names = "ipg", "per";
828 dma-names = "rx", "tx";
833 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
838 clock-names = "ipg", "per";
840 dma-names = "rx", "tx";
845 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
850 clock-names = "ipg", "per";
852 dma-names = "rx", "tx";
857 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
862 clock-names = "ipg", "per";
868 compatible = "fsl,sec-v4.0";
869 #address-cells = <1>;
870 #size-cells = <1>;
876 clock-names = "aclk", "ipg";
879 compatible = "fsl,sec-v4.0-job-ring";
886 compatible = "fsl,sec-v4.0-job-ring";
892 compatible = "fsl,sec-v4.0-job-ring";
898 i2c1: i2c@30a20000 {
899 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
900 #address-cells = <1>;
901 #size-cells = <0>;
908 i2c2: i2c@30a30000 {
909 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
910 #address-cells = <1>;
911 #size-cells = <0>;
918 i2c3: i2c@30a40000 {
919 #address-cells = <1>;
920 #size-cells = <0>;
921 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
928 i2c4: i2c@30a50000 {
929 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
930 #address-cells = <1>;
931 #size-cells = <0>;
939 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
944 clock-names = "ipg", "per";
946 dma-names = "rx", "tx";
951 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
955 #mbox-cells = <2>;
959 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
965 clock-names = "ipg", "ahb", "per";
966 fsl,tuning-start-tap = <20>;
967 fsl,tuning-step = <2>;
968 bus-width = <4>;
973 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
979 clock-names = "ipg", "ahb", "per";
980 fsl,tuning-start-tap = <20>;
981 fsl,tuning-step = <2>;
982 bus-width = <4>;
987 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
993 clock-names = "ipg", "ahb", "per";
994 fsl,tuning-start-tap = <20>;
995 fsl,tuning-step = <2>;
996 bus-width = <4>;
1001 #address-cells = <1>;
1002 #size-cells = <0>;
1003 compatible = "nxp,imx8mm-fspi";
1005 reg-names = "fspi_base", "fspi_mmap";
1009 clock-names = "fspi_en", "fspi";
1013 sdma1: dma-controller@30bd0000 {
1014 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
1019 clock-names = "ipg", "ahb";
1020 #dma-cells = <3>;
1021 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1025 compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1036 clock-names = "ipg", "ahb", "ptp",
1038 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
1042 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
1046 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1047 fsl,num-tx-queues = <3>;
1048 fsl,num-rx-queues = <3>;
1049 nvmem-cells = <&fec_mac_address>;
1050 nvmem-cell-names = "mac-address";
1051 fsl,stop-mode = <&gpr 0x10 3>;
1058 compatible = "fsl,aips-bus", "simple-bus";
1060 #address-cells = <1>;
1061 #size-cells = <1>;
1065 compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif";
1070 clock-names = "pix", "axi", "disp_axi";
1072 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>;
1077 remote-endpoint = <&dsim_from_lcdif>;
1083 compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim";
1087 clock-names = "bus_clk", "sclk_mipi";
1089 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
1093 #address-cells = <1>;
1094 #size-cells = <0>;
1100 remote-endpoint = <&lcdif_to_dsim>;
1114 compatible = "fsl,imx8mn-isi";
1119 clock-names = "axi", "apb";
1120 fsl,blk-ctrl = <&disp_blk_ctrl>;
1121 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>;
1125 #address-cells = <1>;
1126 #size-cells = <0>;
1131 remote-endpoint = <&mipi_csi_out>;
1137 disp_blk_ctrl: blk-ctrl@32e28000 {
1138 compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
1140 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1143 power-domain-names = "bus", "isi",
1144 "lcdif", "mipi-dsi",
1145 "mipi-csi";
1157 clock-names = "disp_axi", "disp_apb",
1159 "lcdif-axi", "lcdif-apb", "lcdif-pix",
1160 "dsi-pclk", "dsi-ref",
1161 "csi-aclk", "csi-pclk";
1162 assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
1167 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
1172 assigned-clock-rates = <266000000>,
1177 #power-domain-cells = <1>;
1180 mipi_csi: mipi-csi@32e30000 {
1181 compatible = "fsl,imx8mm-mipi-csi2";
1184 assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;
1185 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;
1186 assigned-clock-rates = <333000000>;
1187 clock-frequency = <333000000>;
1192 clock-names = "pclk", "wrap", "phy", "axi";
1193 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>;
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1208 remote-endpoint = <&isi_in>;
1215 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
1219 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
1220 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
1223 power-domains = <&pgc_hsiomix>;
1228 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc",
1229 "fsl,imx6q-usbmisc";
1230 #index-cells = <1>;
1235 dma_apbh: dma-controller@33000000 {
1236 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1242 #dma-cells = <1>;
1243 dma-channels = <4>;
1247 gpmi: nand-controller@33002000 {
1248 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
1249 #address-cells = <1>;
1250 #size-cells = <0>;
1252 reg-names = "gpmi-nand", "bch";
1254 interrupt-names = "bch";
1257 clock-names = "gpmi_io", "gpmi_bch_apb";
1259 dma-names = "rx-tx";
1271 clock-names = "reg", "bus", "core", "shader";
1272 assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
1277 assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
1281 assigned-clock-rates = <400000000>,
1286 power-domains = <&pgc_gpumix>;
1289 gic: interrupt-controller@38800000 {
1290 compatible = "arm,gic-v3";
1293 #interrupt-cells = <3>;
1294 interrupt-controller;
1298 ddrc: memory-controller@3d400000 {
1299 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
1301 clock-names = "core", "pll", "alt", "apb";
1308 ddr-pmu@3d800000 {
1309 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
1316 #phy-cells = <0>;
1317 compatible = "usb-nop-xceiv";
1319 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1320 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
1321 clock-names = "main_clk";
1322 power-domains = <&pgc_otg1>;