Lines Matching +full:0 +full:x302c0000
46 #size-cells = <0>;
53 arm,psci-suspend-param = <0x0010033>;
61 A53_0: cpu@0 {
64 reg = <0x0>;
67 i-cache-size = <0x8000>;
70 d-cache-size = <0x8000>;
84 reg = <0x1>;
87 i-cache-size = <0x8000>;
90 d-cache-size = <0x8000>;
102 reg = <0x2>;
105 i-cache-size = <0x8000>;
108 d-cache-size = <0x8000>;
120 reg = <0x3>;
123 i-cache-size = <0x8000>;
126 d-cache-size = <0x8000>;
139 cache-size = <0x80000>;
152 opp-supported-hw = <0xb00>, <0x7>;
160 opp-supported-hw = <0x300>, <0x7>;
168 opp-supported-hw = <0x100>, <0x3>;
176 #clock-cells = <0>;
183 #clock-cells = <0>;
190 #clock-cells = <0>;
197 #clock-cells = <0>;
204 #clock-cells = <0>;
211 #clock-cells = <0>;
269 soc: soc@0 {
273 ranges = <0x0 0x0 0x0 0x3e000000>;
274 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
280 reg = <0x30000000 0x400000>;
289 reg = <0x30000000 0x100000>;
294 reg = <0x30020000 0x10000>;
295 #sound-dai-cells = <0>;
302 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
309 reg = <0x30030000 0x10000>;
310 #sound-dai-cells = <0>;
317 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
324 reg = <0x30050000 0x10000>;
325 #sound-dai-cells = <0>;
332 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
335 fsl,dataline = <0 0xf 0xf>;
341 reg = <0x30060000 0x10000>;
342 #sound-dai-cells = <0>;
349 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
356 reg = <0x30080000 0x10000>;
368 dmas = <&sdma2 24 25 0x80000000>;
370 #sound-dai-cells = <0>;
376 reg = <0x30090000 0x10000>;
393 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
400 reg = <0x300b0000 0x10000>;
401 #sound-dai-cells = <0>;
408 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
415 reg = <0x300c0000 0x10000>;
419 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
420 <&sdma2 18 23 0> , <&sdma2 19 23 0>,
421 <&sdma2 20 23 0> , <&sdma2 21 23 0>,
422 <&sdma2 22 23 0> , <&sdma2 23 23 0>;
436 reg = <0x30200000 0x10000>;
444 gpio-ranges = <&iomuxc 0 10 30>;
449 reg = <0x30210000 0x10000>;
457 gpio-ranges = <&iomuxc 0 40 21>;
462 reg = <0x30220000 0x10000>;
470 gpio-ranges = <&iomuxc 0 61 26>;
475 reg = <0x30230000 0x10000>;
488 reg = <0x30240000 0x10000>;
496 gpio-ranges = <&iomuxc 0 119 30>;
501 reg = <0x30260000 0x10000>;
505 #thermal-sensor-cells = <0>;
510 reg = <0x30280000 0x10000>;
518 reg = <0x30290000 0x10000>;
526 reg = <0x302a0000 0x10000>;
534 reg = <0x302b0000 0x10000>;
545 reg = <0x302c0000 0x10000>;
556 reg = <0x30330000 0x10000>;
561 reg = <0x30340000 0x10000>;
566 reg = <0x30350000 0x10000>;
577 * Fuse Address = (ADDR * 4) + 0x400
580 * +0x10 in Fusemap Description Table (e.g.
581 * reg = <0x4 0x8> describes fuses 0x410 and
582 * 0x420).
584 imx8mn_uid: unique-id@4 { /* 0x410-0x420 */
585 reg = <0x4 0x8>;
588 cpu_speed_grade: speed-grade@10 { /* 0x440 */
589 reg = <0x10 4>;
592 tmu_calib: calib@3c { /* 0x4f0 */
593 reg = <0x3c 4>;
596 fec_mac_address: mac-address@90 { /* 0x640 */
597 reg = <0x90 6>;
603 reg = <0x30360000 0x10000>;
608 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
609 reg = <0x30370000 0x10000>;
612 compatible = "fsl,sec-v4.0-mon-rtc-lp";
614 offset = <0x34>;
622 compatible = "fsl,sec-v4.0-pwrkey";
635 reg = <0x30380000 0x10000>;
655 assigned-clock-rates = <0>, <0>, <0>,
665 reg = <0x30390000 0x10000>;
672 reg = <0x303a0000 0x10000>;
678 #size-cells = <0>;
680 pgc_hsiomix: power-domain@0 {
681 #power-domain-cells = <0>;
687 #power-domain-cells = <0>;
692 #power-domain-cells = <0>;
701 #power-domain-cells = <0>;
708 #power-domain-cells = <0>;
718 reg = <0x30400000 0x400000>;
725 reg = <0x30660000 0x10000>;
736 reg = <0x30670000 0x10000>;
747 reg = <0x30680000 0x10000>;
758 reg = <0x30690000 0x10000>;
769 reg = <0x306a0000 0x20000>;
778 reg = <0x30800000 0x400000>;
787 reg = <0x30800000 0x100000>;
793 #size-cells = <0>;
794 reg = <0x30820000 0x10000>;
799 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
807 #size-cells = <0>;
808 reg = <0x30830000 0x10000>;
821 #size-cells = <0>;
822 reg = <0x30840000 0x10000>;
834 reg = <0x30860000 0x10000>;
839 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
846 reg = <0x30880000 0x10000>;
851 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
858 reg = <0x30890000 0x10000>;
863 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
870 compatible = "fsl,sec-v4.0";
873 reg = <0x30900000 0x40000>;
874 ranges = <0 0x30900000 0x40000>;
881 compatible = "fsl,sec-v4.0-job-ring";
882 reg = <0x1000 0x1000>;
888 compatible = "fsl,sec-v4.0-job-ring";
889 reg = <0x2000 0x1000>;
894 compatible = "fsl,sec-v4.0-job-ring";
895 reg = <0x3000 0x1000>;
903 #size-cells = <0>;
904 reg = <0x30a20000 0x10000>;
913 #size-cells = <0>;
914 reg = <0x30a30000 0x10000>;
922 #size-cells = <0>;
924 reg = <0x30a40000 0x10000>;
933 #size-cells = <0>;
934 reg = <0x30a50000 0x10000>;
942 reg = <0x30a60000 0x10000>;
947 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
954 reg = <0x30aa0000 0x10000>;
962 reg = <0x30b40000 0x10000>;
976 reg = <0x30b50000 0x10000>;
990 reg = <0x30b60000 0x10000>;
1004 #size-cells = <0>;
1006 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1017 reg = <0x30bd0000 0x10000>;
1028 reg = <0x30be0000 0x10000>;
1048 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1053 fsl,stop-mode = <&gpr 0x10 3>;
1061 reg = <0x32c00000 0x400000>;
1068 reg = <0x32e00000 0x10000>;
1086 reg = <0x32e10000 0x400>;
1096 #size-cells = <0>;
1098 port@0 {
1099 reg = <0>;
1117 reg = <0x32e20000 0x8000>;
1128 #size-cells = <0>;
1130 port@0 {
1131 reg = <0>;
1141 reg = <0x32e28000 0x100>;
1184 reg = <0x32e30000 0x1000>;
1200 #size-cells = <0>;
1202 port@0 {
1203 reg = <0>;
1218 reg = <0x32e40000 0x200>;
1224 fsl,usbmisc = <&usbmisc1 0>;
1233 reg = <0x32e40200 0x200>;
1239 reg = <0x33000000 0x2000>;
1252 #size-cells = <0>;
1253 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1260 dmas = <&dma_apbh 0>;
1267 reg = <0x38000000 0x8000>;
1293 reg = <0x38800000 0x10000>,
1294 <0x38880000 0xc0000>;
1302 reg = <0x3d400000 0x400000>;
1312 reg = <0x3d800000 0x400000>;
1318 #phy-cells = <0>;