Lines Matching +full:0 +full:x84
15 reg = <0x00000000 0x40000000 0 0x40000000>;
43 size = <0 0x28000000>;
45 alloc-ranges = <0 0x40000000 0 0x78000000>;
61 pinctrl-0 = <&pinctrl_flexspi>;
64 flash0: flash@0 {
66 reg = <0>;
83 pinctrl-0 = <&pinctrl_i2c1>;
91 reg = <0x1b>;
96 reg = <0x25>;
99 pinctrl-0 = <&pinctrl_pmic>;
211 reg = <0x51>;
218 reg = <0x53>;
225 reg = <0x57>;
238 pinctrl-0 = <&pinctrl_usdhc3>;
257 pinctrl-0 = <&pinctrl_wdog>;
264 fsl,pins = <MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x84>,
265 <MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84>,
266 <MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84>,
267 <MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84>,
268 <MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84>,
269 <MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84>;
273 fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c4>,
274 <MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c4>;
278 fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c4>,
279 <MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c4>;
283 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x84>;
287 fsl,pins = <MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>;
291 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>,
292 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
293 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
294 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
295 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
296 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
297 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
298 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
299 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
300 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
301 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
302 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>;
306 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>,
307 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
308 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
309 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
310 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
311 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
312 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
313 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
314 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
315 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
316 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
317 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>;
321 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>,
322 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
323 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
324 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
325 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
326 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
327 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
328 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
329 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
330 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
331 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
332 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>;
336 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>;