Lines Matching full:assigned
308 assigned-clocks = <&clk IMX8MN_CLK_CLKO1>;
309 assigned-clock-parents = <&clk IMX8MN_CLK_24M>;
310 assigned-clock-rates = <24000000>;
334 assigned-clocks = <&clk IMX8MN_CLK_PDM>;
335 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
336 assigned-clock-rates = <196608000>;
377 assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
378 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
379 assigned-clock-rates = <24576000>;
386 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
387 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
388 assigned-clock-rates = <24576000>;
400 assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
401 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
402 assigned-clock-rates = <24576000>;
409 assigned-clocks = <&clk IMX8MN_CLK_UART1>;
410 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
424 assigned-clocks = <&clk IMX8MN_CLK_UART3>;
425 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
453 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
454 assigned-clock-rates = <200000000>;
466 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
467 assigned-clock-rates = <400000000>;