Lines Matching +full:imx28 +full:- +full:i2c
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/imx8mm-power.h>
11 #include <dt-bindings/reset/imx8mq-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mm-pinfunc.h"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
45 #address-cells = <1>;
46 #size-cells = <0>;
48 idle-states {
49 entry-method = "psci";
51 cpu_pd_wait: cpu-pd-wait {
52 compatible = "arm,idle-state";
53 arm,psci-suspend-param = <0x0010033>;
54 local-timer-stop;
55 entry-latency-us = <1000>;
56 exit-latency-us = <700>;
57 min-residency-us = <2700>;
63 compatible = "arm,cortex-a53";
66 enable-method = "psci";
67 i-cache-size = <0x8000>;
68 i-cache-line-size = <64>;
69 i-cache-sets = <256>;
70 d-cache-size = <0x8000>;
71 d-cache-line-size = <64>;
72 d-cache-sets = <128>;
73 next-level-cache = <&A53_L2>;
74 operating-points-v2 = <&a53_opp_table>;
75 nvmem-cells = <&cpu_speed_grade>;
76 nvmem-cell-names = "speed_grade";
77 cpu-idle-states = <&cpu_pd_wait>;
78 #cooling-cells = <2>;
83 compatible = "arm,cortex-a53";
86 enable-method = "psci";
87 i-cache-size = <0x8000>;
88 i-cache-line-size = <64>;
89 i-cache-sets = <256>;
90 d-cache-size = <0x8000>;
91 d-cache-line-size = <64>;
92 d-cache-sets = <128>;
93 next-level-cache = <&A53_L2>;
94 operating-points-v2 = <&a53_opp_table>;
95 cpu-idle-states = <&cpu_pd_wait>;
96 #cooling-cells = <2>;
101 compatible = "arm,cortex-a53";
104 enable-method = "psci";
105 i-cache-size = <0x8000>;
106 i-cache-line-size = <64>;
107 i-cache-sets = <256>;
108 d-cache-size = <0x8000>;
109 d-cache-line-size = <64>;
110 d-cache-sets = <128>;
111 next-level-cache = <&A53_L2>;
112 operating-points-v2 = <&a53_opp_table>;
113 cpu-idle-states = <&cpu_pd_wait>;
114 #cooling-cells = <2>;
119 compatible = "arm,cortex-a53";
122 enable-method = "psci";
123 i-cache-size = <0x8000>;
124 i-cache-line-size = <64>;
125 i-cache-sets = <256>;
126 d-cache-size = <0x8000>;
127 d-cache-line-size = <64>;
128 d-cache-sets = <128>;
129 next-level-cache = <&A53_L2>;
130 operating-points-v2 = <&a53_opp_table>;
131 cpu-idle-states = <&cpu_pd_wait>;
132 #cooling-cells = <2>;
135 A53_L2: l2-cache0 {
137 cache-level = <2>;
138 cache-unified;
139 cache-size = <0x80000>;
140 cache-line-size = <64>;
141 cache-sets = <512>;
145 a53_opp_table: opp-table {
146 compatible = "operating-points-v2";
147 opp-shared;
149 opp-1200000000 {
150 opp-hz = /bits/ 64 <1200000000>;
151 opp-microvolt = <850000>;
152 opp-supported-hw = <0xe>, <0x7>;
153 clock-latency-ns = <150000>;
154 opp-suspend;
157 opp-1600000000 {
158 opp-hz = /bits/ 64 <1600000000>;
159 opp-microvolt = <950000>;
160 opp-supported-hw = <0xc>, <0x7>;
161 clock-latency-ns = <150000>;
162 opp-suspend;
165 opp-1800000000 {
166 opp-hz = /bits/ 64 <1800000000>;
167 opp-microvolt = <1000000>;
168 opp-supported-hw = <0x8>, <0x3>;
169 clock-latency-ns = <150000>;
170 opp-suspend;
174 osc_32k: clock-osc-32k {
175 compatible = "fixed-clock";
176 #clock-cells = <0>;
177 clock-frequency = <32768>;
178 clock-output-names = "osc_32k";
181 osc_24m: clock-osc-24m {
182 compatible = "fixed-clock";
183 #clock-cells = <0>;
184 clock-frequency = <24000000>;
185 clock-output-names = "osc_24m";
188 clk_ext1: clock-ext1 {
189 compatible = "fixed-clock";
190 #clock-cells = <0>;
191 clock-frequency = <133000000>;
192 clock-output-names = "clk_ext1";
195 clk_ext2: clock-ext2 {
196 compatible = "fixed-clock";
197 #clock-cells = <0>;
198 clock-frequency = <133000000>;
199 clock-output-names = "clk_ext2";
202 clk_ext3: clock-ext3 {
203 compatible = "fixed-clock";
204 #clock-cells = <0>;
205 clock-frequency = <133000000>;
206 clock-output-names = "clk_ext3";
209 clk_ext4: clock-ext4 {
210 compatible = "fixed-clock";
211 #clock-cells = <0>;
212 clock-frequency = <133000000>;
213 clock-output-names = "clk_ext4";
217 compatible = "arm,psci-1.0";
222 compatible = "arm,cortex-a53-pmu";
228 compatible = "arm,armv8-timer";
230 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
233 clock-frequency = <8000000>;
234 arm,no-tick-in-suspend;
237 thermal-zones {
238 cpu-thermal {
239 polling-delay-passive = <250>;
240 polling-delay = <2000>;
241 thermal-sensors = <&tmu>;
256 cooling-maps {
259 cooling-device =
270 #phy-cells = <0>;
271 compatible = "usb-nop-xceiv";
273 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
274 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
275 clock-names = "main_clk";
276 power-domains = <&pgc_otg1>;
280 #phy-cells = <0>;
281 compatible = "usb-nop-xceiv";
283 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
284 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
285 clock-names = "main_clk";
286 power-domains = <&pgc_otg2>;
290 compatible = "fsl,imx8mm-soc", "simple-bus";
291 #address-cells = <1>;
292 #size-cells = <1>;
294 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
295 nvmem-cells = <&imx8mm_uid>;
296 nvmem-cell-names = "soc_unique_id";
299 compatible = "fsl,aips-bus", "simple-bus";
301 #address-cells = <1>;
302 #size-cells = <1>;
305 spba2: spba-bus@30000000 {
306 compatible = "fsl,spba-bus", "simple-bus";
307 #address-cells = <1>;
308 #size-cells = <1>;
313 #sound-dai-cells = <0>;
314 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
320 clock-names = "bus", "mclk1", "mclk2", "mclk3";
322 dma-names = "rx", "tx";
327 #sound-dai-cells = <0>;
328 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
334 clock-names = "bus", "mclk1", "mclk2", "mclk3";
336 dma-names = "rx", "tx";
341 #sound-dai-cells = <0>;
342 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
348 clock-names = "bus", "mclk1", "mclk2", "mclk3";
350 dma-names = "rx", "tx";
355 #sound-dai-cells = <0>;
356 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
362 clock-names = "bus", "mclk1", "mclk2", "mclk3";
364 dma-names = "rx", "tx";
369 #sound-dai-cells = <0>;
370 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
376 clock-names = "bus", "mclk1", "mclk2", "mclk3";
378 dma-names = "rx", "tx";
382 micfil: audio-controller@30080000 {
383 compatible = "fsl,imx8mm-micfil";
394 clock-names = "ipg_clk", "ipg_clk_app",
397 dma-names = "rx";
398 #sound-dai-cells = <0>;
403 compatible = "fsl,imx35-spdif";
416 clock-names = "core", "rxtx0",
422 dma-names = "rx", "tx";
428 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
433 gpio-controller;
434 #gpio-cells = <2>;
435 interrupt-controller;
436 #interrupt-cells = <2>;
437 gpio-ranges = <&iomuxc 0 10 30>;
441 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
446 gpio-controller;
447 #gpio-cells = <2>;
448 interrupt-controller;
449 #interrupt-cells = <2>;
450 gpio-ranges = <&iomuxc 0 40 21>;
454 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
459 gpio-controller;
460 #gpio-cells = <2>;
461 interrupt-controller;
462 #interrupt-cells = <2>;
463 gpio-ranges = <&iomuxc 0 61 26>;
467 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
472 gpio-controller;
473 #gpio-cells = <2>;
474 interrupt-controller;
475 #interrupt-cells = <2>;
476 gpio-ranges = <&iomuxc 0 87 32>;
480 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
485 gpio-controller;
486 #gpio-cells = <2>;
487 interrupt-controller;
488 #interrupt-cells = <2>;
489 gpio-ranges = <&iomuxc 0 119 30>;
493 compatible = "fsl,imx8mm-tmu";
496 nvmem-cells = <&tmu_calib>;
497 nvmem-cell-names = "calib";
498 #thermal-sensor-cells = <0>;
502 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
510 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
518 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
525 sdma2: dma-controller@302c0000 {
526 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
531 clock-names = "ipg", "ahb";
532 #dma-cells = <3>;
533 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
536 sdma3: dma-controller@302b0000 {
537 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
542 clock-names = "ipg", "ahb";
543 #dma-cells = <3>;
544 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
548 compatible = "fsl,imx8mm-iomuxc";
553 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
558 compatible = "fsl,imx8mm-ocotp", "syscon";
562 #address-cells = <1>;
563 #size-cells = <1>;
578 imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
582 cpu_speed_grade: speed-grade@10 { /* 0x440 */
590 fec_mac_address: mac-address@90 { /* 0x640 */
595 anatop: clock-controller@30360000 {
596 compatible = "fsl,imx8mm-anatop";
598 #clock-cells = <1>;
602 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
605 snvs_rtc: snvs-rtc-lp {
606 compatible = "fsl,sec-v4.0-mon-rtc-lp";
612 clock-names = "snvs-rtc";
615 snvs_pwrkey: snvs-powerkey {
616 compatible = "fsl,sec-v4.0-pwrkey";
620 clock-names = "snvs-pwrkey";
622 wakeup-source;
626 snvs_lpgpr: snvs-lpgpr {
627 compatible = "fsl,imx8mm-snvs-lpgpr",
628 "fsl,imx7d-snvs-lpgpr";
632 clk: clock-controller@30380000 {
633 compatible = "fsl,imx8mm-ccm";
637 #clock-cells = <1>;
640 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
642 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
649 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
653 assigned-clock-rates = <0>, <0>, <0>,
660 src: reset-controller@30390000 {
661 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
664 #reset-cells = <1>;
668 compatible = "fsl,imx8mm-gpc";
671 interrupt-parent = <&gic>;
672 interrupt-controller;
673 #interrupt-cells = <3>;
676 #address-cells = <1>;
677 #size-cells = <0>;
679 pgc_hsiomix: power-domain@0 {
680 #power-domain-cells = <0>;
683 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
684 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
687 pgc_pcie: power-domain@1 {
688 #power-domain-cells = <0>;
690 power-domains = <&pgc_hsiomix>;
694 pgc_otg1: power-domain@2 {
695 #power-domain-cells = <0>;
699 pgc_otg2: power-domain@3 {
700 #power-domain-cells = <0>;
704 pgc_gpumix: power-domain@4 {
705 #power-domain-cells = <0>;
709 assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
711 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
713 assigned-clock-rates = <800000000>, <400000000>;
716 pgc_gpu: power-domain@5 {
717 #power-domain-cells = <0>;
724 power-domains = <&pgc_gpumix>;
727 pgc_vpumix: power-domain@6 {
728 #power-domain-cells = <0>;
731 assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
732 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
735 pgc_vpu_g1: power-domain@7 {
736 #power-domain-cells = <0>;
740 pgc_vpu_g2: power-domain@8 {
741 #power-domain-cells = <0>;
745 pgc_vpu_h1: power-domain@9 {
746 #power-domain-cells = <0>;
750 pgc_dispmix: power-domain@10 {
751 #power-domain-cells = <0>;
755 assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
757 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
759 assigned-clock-rates = <500000000>, <200000000>;
762 pgc_mipi: power-domain@11 {
763 #power-domain-cells = <0>;
771 compatible = "fsl,aips-bus", "simple-bus";
773 #address-cells = <1>;
774 #size-cells = <1>;
778 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
783 clock-names = "ipg", "per";
784 #pwm-cells = <3>;
789 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
794 clock-names = "ipg", "per";
795 #pwm-cells = <3>;
800 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
805 clock-names = "ipg", "per";
806 #pwm-cells = <3>;
811 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
816 clock-names = "ipg", "per";
817 #pwm-cells = <3>;
822 compatible = "nxp,sysctr-timer";
826 clock-names = "per";
831 compatible = "fsl,aips-bus", "simple-bus";
833 #address-cells = <1>;
834 #size-cells = <1>;
838 spba1: spba-bus@30800000 {
839 compatible = "fsl,spba-bus", "simple-bus";
840 #address-cells = <1>;
841 #size-cells = <1>;
846 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
847 #address-cells = <1>;
848 #size-cells = <0>;
853 clock-names = "ipg", "per";
855 dma-names = "rx", "tx";
860 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
861 #address-cells = <1>;
862 #size-cells = <0>;
867 clock-names = "ipg", "per";
869 dma-names = "rx", "tx";
874 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
875 #address-cells = <1>;
876 #size-cells = <0>;
881 clock-names = "ipg", "per";
883 dma-names = "rx", "tx";
888 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
893 clock-names = "ipg", "per";
895 dma-names = "rx", "tx";
900 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
905 clock-names = "ipg", "per";
907 dma-names = "rx", "tx";
912 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
917 clock-names = "ipg", "per";
923 compatible = "fsl,sec-v4.0";
924 #address-cells = <1>;
925 #size-cells = <1>;
931 clock-names = "aclk", "ipg";
934 compatible = "fsl,sec-v4.0-job-ring";
941 compatible = "fsl,sec-v4.0-job-ring";
947 compatible = "fsl,sec-v4.0-job-ring";
953 i2c1: i2c@30a20000 {
954 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
955 #address-cells = <1>;
956 #size-cells = <0>;
963 i2c2: i2c@30a30000 {
964 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
965 #address-cells = <1>;
966 #size-cells = <0>;
973 i2c3: i2c@30a40000 {
974 #address-cells = <1>;
975 #size-cells = <0>;
976 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
983 i2c4: i2c@30a50000 {
984 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
985 #address-cells = <1>;
986 #size-cells = <0>;
994 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
999 clock-names = "ipg", "per";
1001 dma-names = "rx", "tx";
1006 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
1010 #mbox-cells = <2>;
1014 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1020 clock-names = "ipg", "ahb", "per";
1021 fsl,tuning-start-tap = <20>;
1022 fsl,tuning-step = <2>;
1023 bus-width = <4>;
1028 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1034 clock-names = "ipg", "ahb", "per";
1035 fsl,tuning-start-tap = <20>;
1036 fsl,tuning-step = <2>;
1037 bus-width = <4>;
1042 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1048 clock-names = "ipg", "ahb", "per";
1049 fsl,tuning-start-tap = <20>;
1050 fsl,tuning-step = <2>;
1051 bus-width = <4>;
1056 #address-cells = <1>;
1057 #size-cells = <0>;
1058 compatible = "nxp,imx8mm-fspi";
1060 reg-names = "fspi_base", "fspi_mmap";
1064 clock-names = "fspi_en", "fspi";
1068 sdma1: dma-controller@30bd0000 {
1069 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
1074 clock-names = "ipg", "ahb";
1075 #dma-cells = <3>;
1076 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1080 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1091 clock-names = "ipg", "ahb", "ptp",
1093 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
1097 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
1101 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1102 fsl,num-tx-queues = <3>;
1103 fsl,num-rx-queues = <3>;
1104 nvmem-cells = <&fec_mac_address>;
1105 nvmem-cell-names = "mac-address";
1106 fsl,stop-mode = <&gpr 0x10 3>;
1113 compatible = "fsl,aips-bus", "simple-bus";
1115 #address-cells = <1>;
1116 #size-cells = <1>;
1120 compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif";
1125 clock-names = "pix", "axi", "disp_axi";
1126 assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
1129 assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
1132 assigned-clock-rates = <24000000>, <500000000>, <200000000>;
1134 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
1139 remote-endpoint = <&dsim_from_lcdif>;
1145 compatible = "fsl,imx8mm-mipi-dsim";
1149 clock-names = "bus_clk", "sclk_mipi";
1150 assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>;
1151 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>;
1153 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
1157 #address-cells = <1>;
1158 #size-cells = <0>;
1164 remote-endpoint = <&lcdif_to_dsim>;
1178 compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
1182 clock-names = "mclk";
1183 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
1188 remote-endpoint = <&imx8mm_mipi_csi_out>;
1193 disp_blk_ctrl: blk-ctrl@32e28000 {
1194 compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
1196 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1199 power-domain-names = "bus", "csi-bridge",
1200 "lcdif", "mipi-dsi",
1201 "mipi-csi";
1212 clock-names = "csi-bridge-axi","csi-bridge-apb",
1213 "csi-bridge-core", "lcdif-axi",
1214 "lcdif-apb", "lcdif-pix",
1215 "dsi-pclk", "dsi-ref",
1216 "csi-aclk", "csi-pclk";
1217 #power-domain-cells = <1>;
1220 mipi_csi: mipi-csi@32e30000 {
1221 compatible = "fsl,imx8mm-mipi-csi2";
1224 assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>;
1225 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>;
1227 clock-frequency = <333000000>;
1232 clock-names = "pclk", "wrap", "phy", "axi";
1233 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>;
1237 #address-cells = <1>;
1238 #size-cells = <0>;
1248 remote-endpoint = <&csi_in>;
1255 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
1259 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1260 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1263 power-domains = <&pgc_hsiomix>;
1268 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
1269 "fsl,imx6q-usbmisc";
1270 #index-cells = <1>;
1275 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
1279 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1280 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1283 power-domains = <&pgc_hsiomix>;
1288 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
1289 "fsl,imx6q-usbmisc";
1290 #index-cells = <1>;
1294 pcie_phy: pcie-phy@32f00000 {
1295 compatible = "fsl,imx8mm-pcie-phy";
1298 clock-names = "ref";
1299 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
1300 assigned-clock-rates = <100000000>;
1301 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
1303 reset-names = "pciephy";
1304 #phy-cells = <0>;
1309 dma_apbh: dma-controller@33000000 {
1310 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1316 #dma-cells = <1>;
1317 dma-channels = <4>;
1321 gpmi: nand-controller@33002000 {
1322 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1323 #address-cells = <1>;
1324 #size-cells = <0>;
1326 reg-names = "gpmi-nand", "bch";
1328 interrupt-names = "bch";
1331 clock-names = "gpmi_io", "gpmi_bch_apb";
1333 dma-names = "rx-tx";
1338 compatible = "fsl,imx8mm-pcie";
1340 reg-names = "dbi", "config";
1341 #address-cells = <3>;
1342 #size-cells = <2>;
1344 bus-range = <0x00 0xff>;
1346 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1347 num-lanes = <1>;
1348 num-viewport = <4>;
1350 interrupt-names = "msi";
1351 #interrupt-cells = <1>;
1352 interrupt-map-mask = <0 0 0 0x7>;
1353 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1357 fsl,max-link-speed = <2>;
1358 linux,pci-domain = <0>;
1362 clock-names = "pcie", "pcie_bus", "pcie_aux";
1363 power-domains = <&pgc_pcie>;
1366 reset-names = "apps", "turnoff";
1368 phy-names = "pcie-phy";
1372 pcie0_ep: pcie-ep@33800000 {
1373 compatible = "fsl,imx8mm-pcie-ep";
1378 reg-names = "dbi", "addr_space", "dbi2", "atu";
1379 num-lanes = <1>;
1381 interrupt-names = "dma";
1382 fsl,max-link-speed = <2>;
1386 clock-names = "pcie", "pcie_bus", "pcie_aux";
1387 power-domains = <&pgc_pcie>;
1390 reset-names = "apps", "turnoff";
1392 phy-names = "pcie-phy";
1393 num-ib-windows = <4>;
1394 num-ob-windows = <4>;
1406 clock-names = "reg", "bus", "core", "shader";
1407 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
1409 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1410 assigned-clock-rates = <0>, <800000000>;
1411 power-domains = <&pgc_gpu>;
1421 clock-names = "reg", "bus", "core";
1422 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
1424 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1425 assigned-clock-rates = <0>, <800000000>;
1426 power-domains = <&pgc_gpu>;
1429 vpu_g1: video-codec@38300000 {
1430 compatible = "nxp,imx8mm-vpu-g1";
1434 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
1437 vpu_g2: video-codec@38310000 {
1438 compatible = "nxp,imx8mq-vpu-g2";
1442 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
1445 vpu_blk_ctrl: blk-ctrl@38330000 {
1446 compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
1448 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1450 power-domain-names = "bus", "g1", "g2", "h1";
1454 clock-names = "g1", "g2", "h1";
1455 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
1457 assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
1459 assigned-clock-rates = <600000000>,
1461 #power-domain-cells = <1>;
1464 gic: interrupt-controller@38800000 {
1465 compatible = "arm,gic-v3";
1468 #interrupt-cells = <3>;
1469 interrupt-controller;
1473 ddrc: memory-controller@3d400000 {
1474 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
1476 clock-names = "core", "pll", "alt", "apb";
1483 ddr-pmu@3d800000 {
1484 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";