Lines Matching +full:buck3 +full:- +full:in +full:- +full:supply
1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
3 * Copyright 2020-2021 TQ-Systems GmbH
6 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 model = "TQ-Systems GmbH i.MX8MM TQMa8MxML";
11 compatible = "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
19 /* e-MMC IO, needed for HS modes */
20 reg_vcc1v8: regulator-vcc1v8 {
21 compatible = "regulator-fixed";
22 regulator-name = "TQMA8MXML_VCC1V8";
23 regulator-min-microvolt = <1800000>;
24 regulator-max-microvolt = <1800000>;
28 reg_vcc3v3: regulator-vcc3v3 {
29 compatible = "regulator-fixed";
30 regulator-name = "TQMA8MXML_VCC3V3";
31 regulator-min-microvolt = <3300000>;
32 regulator-max-microvolt = <3300000>;
35 reserved-memory {
36 #address-cells = <2>;
37 #size-cells = <2>;
42 compatible = "shared-dma-pool";
46 /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
47 alloc-ranges = <0 0x40000000 0 0x78000000>;
48 linux,cma-default;
54 cpu-supply = <&buck2_reg>;
58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_flexspi>;
63 compatible = "jedec,spi-nor";
65 spi-max-frequency = <84000000>;
66 spi-tx-bus-width = <1>;
67 spi-rx-bus-width = <4>;
70 compatible = "fixed-partitions";
71 #address-cells = <1>;
72 #size-cells = <1>;
86 pinctrl-names = "default", "gpio";
87 pinctrl-0 = <&pinctrl_i2c1>;
88 pinctrl-1 = <&pinctrl_i2c1_gpio>;
89 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
90 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
93 sensor0: temperature-sensor@1b {
94 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
103 pinctrl-0 = <&pinctrl_pmic>;
104 pinctrl-names = "default";
105 interrupt-parent = <&gpio1>;
111 regulator-name = "BUCK1";
112 regulator-min-microvolt = <850000>;
113 regulator-max-microvolt = <850000>;
114 regulator-boot-on;
115 regulator-always-on;
116 regulator-ramp-delay = <3125>;
121 regulator-name = "BUCK2";
122 regulator-min-microvolt = <850000>;
123 regulator-max-microvolt = <1000000>;
124 regulator-boot-on;
125 regulator-always-on;
126 nxp,dvs-run-voltage = <950000>;
127 nxp,dvs-standby-voltage = <850000>;
128 regulator-ramp-delay = <3125>;
132 buck3_reg: BUCK3 {
133 regulator-name = "BUCK3";
134 regulator-min-microvolt = <850000>;
135 regulator-max-microvolt = <950000>;
136 regulator-boot-on;
137 regulator-always-on;
138 regulator-ramp-delay = <3125>;
141 /* VCC3V3 -> VMMC, ... must not be changed */
143 regulator-name = "BUCK4";
144 regulator-min-microvolt = <3300000>;
145 regulator-max-microvolt = <3300000>;
146 regulator-boot-on;
147 regulator-always-on;
150 /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
152 regulator-name = "BUCK5";
153 regulator-min-microvolt = <1800000>;
154 regulator-max-microvolt = <1800000>;
155 regulator-boot-on;
156 regulator-always-on;
159 /* V_1V1 -> RAM, ... must not be changed */
161 regulator-name = "BUCK6";
162 regulator-min-microvolt = <1100000>;
163 regulator-max-microvolt = <1100000>;
164 regulator-boot-on;
165 regulator-always-on;
170 regulator-name = "LDO1";
171 regulator-min-microvolt = <1800000>;
172 regulator-max-microvolt = <1800000>;
173 regulator-boot-on;
174 regulator-always-on;
179 regulator-name = "LDO2";
180 regulator-min-microvolt = <800000>;
181 regulator-max-microvolt = <850000>;
182 regulator-boot-on;
183 regulator-always-on;
188 regulator-name = "LDO3";
189 regulator-min-microvolt = <1800000>;
190 regulator-max-microvolt = <1800000>;
191 regulator-boot-on;
192 regulator-always-on;
197 regulator-name = "LDO4";
198 regulator-min-microvolt = <900000>;
199 regulator-max-microvolt = <900000>;
200 regulator-boot-on;
201 regulator-always-on;
204 /* VCC SD IO - switched using SD2 VSELECT */
206 regulator-name = "LDO5";
207 regulator-min-microvolt = <1800000>;
208 regulator-max-microvolt = <3300000>;
217 quartz-load-femtofarads = <7000>;
222 read-only;
225 vcc-supply = <®_vcc3v3>;
232 vcc-supply = <®_vcc3v3>;
237 vddcore-supply = <&ldo4_reg>;
238 vddio-supply = <&ldo3_reg>;
242 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
243 fsl,clkreq-unsupported;
247 pinctrl-names = "default", "state_100mhz", "state_200mhz";
248 pinctrl-0 = <&pinctrl_usdhc3>;
249 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
250 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
251 bus-width = <8>;
252 non-removable;
253 no-sd;
254 no-sdio;
255 vmmc-supply = <®_vcc3v3>;
256 vqmmc-supply = <®_vcc1v8>;
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_wdog>;
268 fsl,ext-reset-output;
312 /* option USDHC3_RESET_B not defined, only in RM */
316 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
328 /* option USDHC3_RESET_B not defined, only in RM */
332 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
344 /* option USDHC3_RESET_B not defined, only in RM */