Lines Matching +full:imx7ulp +full:- +full:lpi2c
1 // SPDX-License-Identifier: GPL-2.0-only and MIT
8 compatible = "simple-bus";
9 interrupt-parent = <&irqsteer_mipi1>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 irqsteer_mipi1: interrupt-controller@57220000 {
15 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
18 interrupt-controller;
19 interrupt-parent = <&gic>;
20 #interrupt-cells = <1>;
22 clock-names = "ipg";
23 power-domains = <&pd IMX_SC_R_MIPI_1>;
25 fsl,num-irqs = <32>;
28 mipi1_lis_lpcg: clock-controller@57223000 {
29 compatible = "fsl,imx8qxp-lpcg";
31 #clock-cells = <1>;
33 clock-indices = <IMX_LPCG_CLK_0>;
34 clock-output-names = "mipi1_lis_lpcg_ipg_clk";
35 power-domains = <&pd IMX_SC_R_MIPI_1>;
38 mipi1_pwm_lpcg: clock-controller@5722300c {
39 compatible = "fsl,imx8qxp-lpcg";
41 #clock-cells = <1>;
44 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
45 clock-output-names = "mipi1_pwm_lpcg_clk",
47 power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
50 mipi1_i2c0_lpcg_clk: clock-controller@5722301c {
51 compatible = "fsl,imx8qxp-lpcg";
53 #clock-cells = <1>;
55 clock-indices = <IMX_LPCG_CLK_0>;
56 clock-output-names = "mipi1_i2c0_lpcg_clk";
57 power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
60 mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {
61 compatible = "fsl,imx8qxp-lpcg";
63 #clock-cells = <1>;
65 clock-indices = <IMX_LPCG_CLK_0>;
66 clock-output-names = "mipi1_i2c0_lpcg_ipg_clk";
67 power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
70 mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {
71 compatible = "fsl,imx8qxp-lpcg";
73 #clock-cells = <1>;
75 clock-indices = <IMX_LPCG_CLK_0>;
76 clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk";
77 power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
80 mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {
81 compatible = "fsl,imx8qxp-lpcg";
83 #clock-cells = <1>;
85 clock-indices = <IMX_LPCG_CLK_0>;
86 clock-output-names = "mipi1_i2c1_lpcg_ipg_clk";
87 power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
90 mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {
91 compatible = "fsl,imx8qxp-lpcg";
93 #clock-cells = <1>;
95 clock-indices = <IMX_LPCG_CLK_0>;
96 clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk";
97 power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
100 mipi1_i2c1_lpcg_clk: clock-controller@5722302c {
101 compatible = "fsl,imx8qxp-lpcg";
103 #clock-cells = <1>;
105 clock-indices = <IMX_LPCG_CLK_0>;
106 clock-output-names = "mipi1_i2c1_lpcg_clk";
107 power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
111 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
115 clock-names = "ipg", "per";
116 assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
117 assigned-clock-rates = <24000000>;
118 #pwm-cells = <3>;
119 power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
124 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
126 #address-cells = <1>;
127 #size-cells = <0>;
129 interrupt-parent = <&irqsteer_mipi1>;
132 clock-names = "per", "ipg";
133 assigned-clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
134 assigned-clock-rates = <24000000>;
135 power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;