Lines Matching +full:imx7ulp +full:- +full:lpi2c
1 // SPDX-License-Identifier: GPL-2.0-only and MIT
8 compatible = "simple-bus";
9 interrupt-parent = <&irqsteer_mipi0>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 irqsteer_mipi0: interrupt-controller@56220000 {
15 compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer";
18 interrupt-controller;
19 interrupt-parent = <&gic>;
20 #interrupt-cells = <1>;
22 clock-names = "ipg";
23 power-domains = <&pd IMX_SC_R_MIPI_0>;
25 fsl,num-irqs = <32>;
28 mipi0_lis_lpcg: clock-controller@56223000 {
29 compatible = "fsl,imx8qxp-lpcg";
31 #clock-cells = <1>;
32 power-domains = <&pd IMX_SC_R_MIPI_0>;
35 mipi0_pwm_lpcg: clock-controller@5622300c {
36 compatible = "fsl,imx8qxp-lpcg";
38 #clock-cells = <1>;
39 power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
42 mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 {
43 compatible = "fsl,imx8qxp-lpcg";
45 #clock-cells = <1>;
47 clock-indices = <IMX_LPCG_CLK_0>;
48 clock-output-names = "mipi0_i2c0_lpcg_ipg_clk";
49 power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
52 mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 {
53 compatible = "fsl,imx8qxp-lpcg";
55 #clock-cells = <1>;
57 clock-indices = <IMX_LPCG_CLK_0>;
58 clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk";
59 power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
62 mipi0_i2c0_lpcg_clk: clock-controller@5622301c {
63 compatible = "fsl,imx8qxp-lpcg";
65 #clock-cells = <1>;
67 clock-indices = <IMX_LPCG_CLK_0>;
68 clock-output-names = "mipi0_i2c0_lpcg_clk";
69 power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
72 mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 {
73 compatible = "fsl,imx8qxp-lpcg";
75 #clock-cells = <1>;
77 clock-indices = <IMX_LPCG_CLK_0>;
78 clock-output-names = "mipi0_i2c1_lpcg_ipg_clk";
79 power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
82 mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 {
83 compatible = "fsl,imx8qxp-lpcg";
85 #clock-cells = <1>;
87 clock-indices = <IMX_LPCG_CLK_0>;
88 clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk";
89 power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
92 mipi0_i2c1_lpcg_clk: clock-controller@5622302c {
93 compatible = "fsl,imx8qxp-lpcg";
95 #clock-cells = <1>;
97 clock-indices = <IMX_LPCG_CLK_0>;
98 clock-output-names = "mipi0_i2c1_lpcg_clk";
99 power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
103 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
107 clock-names = "ipg", "per";
108 assigned-clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>;
109 assigned-clock-rates = <24000000>;
110 #pwm-cells = <3>;
111 power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
116 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
118 #address-cells = <1>;
119 #size-cells = <0>;
123 clock-names = "per", "ipg";
124 assigned-clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
125 assigned-clock-rates = <24000000>;
126 power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;