Lines Matching +full:imx7ulp +full:- +full:lpi2c
1 // SPDX-License-Identifier: GPL-2.0-only and MIT
8 compatible = "simple-bus";
9 interrupt-parent = <&irqsteer_lvds1>;
10 #address-cells = <1>;
11 #size-cells = <1>;
14 irqsteer_lvds1: interrupt-controller@57240000 {
15 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
18 interrupt-controller;
19 interrupt-parent = <&gic>;
20 #interrupt-cells = <1>;
22 clock-names = "ipg";
23 power-domains = <&pd IMX_SC_R_LVDS_1>;
25 fsl,num-irqs = <32>;
28 lvds1_lis_lpcg: clock-controller@57243000 {
29 compatible = "fsl,imx8qxp-lpcg";
31 #clock-cells = <1>;
33 clock-indices = <IMX_LPCG_CLK_4>;
34 clock-output-names = "lvds1_lis_lpcg_ipg_clk";
35 power-domains = <&pd IMX_SC_R_LVDS_1>;
38 lvds1_pwm_lpcg: clock-controller@5724300c {
39 compatible = "fsl,imx8qxp-lpcg";
41 #clock-cells = <1>;
44 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
45 clock-output-names = "lvds1_pwm_lpcg_clk",
47 power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
50 lvds1_i2c0_lpcg: clock-controller@57243010 {
51 compatible = "fsl,imx8qxp-lpcg";
53 #clock-cells = <1>;
56 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
57 clock-output-names = "lvds1_i2c0_lpcg_clk",
59 power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
62 lvds1_i2c1_lpcg: clock-controller@57243014 {
63 compatible = "fsl,imx8qxp-lpcg";
65 #clock-cells = <1>;
68 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
69 clock-output-names = "lvds1_i2c1_lpcg_clk",
71 power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
75 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
79 clock-names = "ipg", "per";
80 assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>;
81 assigned-clock-rates = <24000000>;
82 #pwm-cells = <3>;
83 power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
88 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
90 #address-cells = <1>;
91 #size-cells = <0>;
95 clock-names = "per", "ipg";
96 assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
97 assigned-clock-rates = <24000000>;
98 power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
103 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
108 clock-names = "per", "ipg";
109 assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
110 assigned-clock-rates = <24000000>;
111 power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;