Lines Matching +full:imx7ulp +full:- +full:lpi2c
1 // SPDX-License-Identifier: GPL-2.0-only and MIT
8 compatible = "simple-bus";
9 #address-cells = <1>;
10 #size-cells = <1>;
13 qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 {
14 compatible = "fsl,imx8qxp-lpcg";
16 #clock-cells = <1>;
17 clock-output-names = "lvds0_lis_lpcg_ipg_clk";
18 power-domains = <&pd IMX_SC_R_MIPI_1>;
21 qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c {
22 compatible = "fsl,imx8qxp-lpcg";
24 #clock-cells = <1>;
25 clock-output-names = "lvds0_pwm_lpcg_clk",
28 power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
31 qm_lvds0_i2c0_lpcg: qxp_mipi1_i2c0_lpcg: clock-controller@56243010 {
32 compatible = "fsl,imx8qxp-lpcg";
34 #clock-cells = <1>;
35 clock-output-names = "lvds0_i2c0_lpcg_clk",
37 power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
41 compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
43 clock-names = "ipg", "per";
44 assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
45 assigned-clock-rates = <24000000>;
46 #pwm-cells = <3>;
47 power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
52 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
54 #address-cells = <1>;
55 #size-cells = <0>;
57 clock-names = "per", "ipg";
58 assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
59 assigned-clock-rates = <24000000>;
60 power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;