Lines Matching +full:clock +full:- +full:controller
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2021 NXP
6 img_ipg_clk: clock-img-ipg {
7 compatible = "fixed-clock";
8 #clock-cells = <0>;
9 clock-frequency = <200000000>;
10 clock-output-names = "img_ipg_clk";
13 img_pxl_clk: clock-img-pxl {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <600000000>;
17 clock-output-names = "img_pxl_clk";
21 compatible = "simple-bus";
22 #address-cells = <1>;
23 #size-cells = <1>;
44 clock-names = "per0", "per1", "per2", "per3",
46 interrupt-parent = <&gic>;
47 power-domains = <&pd IMX_SC_R_ISI_CH0>,
59 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
61 #interrupt-cells = <1>;
62 interrupt-controller;
65 clock-names = "ipg";
66 interrupt-parent = <&gic>;
67 power-domains = <&pd IMX_SC_R_CSI_0>;
69 fsl,num-irqs = <32>;
74 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
76 #interrupt-cells = <2>;
77 interrupt-controller;
79 #gpio-cells = <2>;
80 gpio-controller;
81 interrupt-parent = <&irqsteer_csi0>;
82 power-domains = <&pd IMX_SC_R_CSI_0>;
85 csi0_core_lpcg: clock-controller@58223018 {
86 compatible = "fsl,imx8qxp-lpcg";
89 #clock-cells = <1>;
90 clock-indices = <IMX_LPCG_CLK_4>;
91 clock-output-names = "csi0_lpcg_core_clk";
92 power-domains = <&pd IMX_SC_R_ISI_CH0>;
95 csi0_esc_lpcg: clock-controller@5822301c {
96 compatible = "fsl,imx8qxp-lpcg";
99 #clock-cells = <1>;
100 clock-indices = <IMX_LPCG_CLK_4>;
101 clock-output-names = "csi0_lpcg_esc_clk";
102 power-domains = <&pd IMX_SC_R_ISI_CH0>;
106 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
111 clock-names = "per", "ipg";
112 assigned-clocks = <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>;
113 assigned-clock-rates = <24000000>;
114 interrupt-parent = <&irqsteer_csi0>;
115 power-domains = <&pd IMX_SC_R_CSI_0_I2C_0>;
120 compatible = "fsl,imx8qxp-mipi-csi2";
126 clock-names = "core", "esc", "ui";
127 assigned-clocks = <&csi0_core_lpcg IMX_LPCG_CLK_4>,
129 assigned-clock-rates = <360000000>, <72000000>;
130 power-domains = <&pd IMX_SC_R_ISI_CH0>;
136 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
138 #interrupt-cells = <1>;
139 interrupt-controller;
142 clock-names = "ipg";
143 interrupt-parent = <&gic>;
144 power-domains = <&pd IMX_SC_R_CSI_1>;
146 fsl,num-irqs = <32>;
151 compatible = "fsl,imx8qm-gpio", "fsl,imx35-gpio";
153 #interrupt-cells = <2>;
154 interrupt-controller;
156 #gpio-cells = <2>;
157 gpio-controller;
158 interrupt-parent = <&irqsteer_csi1>;
159 power-domains = <&pd IMX_SC_R_CSI_1>;
162 csi1_core_lpcg: clock-controller@58243018 {
163 compatible = "fsl,imx8qxp-lpcg";
166 #clock-cells = <1>;
167 clock-indices = <IMX_LPCG_CLK_4>;
168 clock-output-names = "csi1_lpcg_core_clk";
169 power-domains = <&pd IMX_SC_R_ISI_CH0>;
172 csi1_esc_lpcg: clock-controller@5824301c {
173 compatible = "fsl,imx8qxp-lpcg";
176 #clock-cells = <1>;
177 clock-indices = <IMX_LPCG_CLK_4>;
178 clock-output-names = "csi1_lpcg_esc_clk";
179 power-domains = <&pd IMX_SC_R_ISI_CH0>;
183 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
188 clock-names = "per", "ipg";
189 assigned-clocks = <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>;
190 assigned-clock-rates = <24000000>;
191 interrupt-parent = <&irqsteer_csi1>;
192 power-domains = <&pd IMX_SC_R_CSI_1_I2C_0>;
197 compatible = "fsl,imx8qxp-mipi-csi2";
203 clock-names = "core", "esc", "ui";
204 assigned-clocks = <&csi1_core_lpcg IMX_LPCG_CLK_4>,
206 assigned-clock-rates = <360000000>, <72000000>;
207 power-domains = <&pd IMX_SC_R_ISI_CH0>;
213 compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
215 #interrupt-cells = <1>;
216 interrupt-controller;
219 clock-names = "ipg";
220 interrupt-parent = <&gic>;
221 power-domains = <&pd IMX_SC_R_PI_0>;
223 fsl,num-irqs = <32>;
227 pi0_ipg_lpcg: clock-controller@58263004 {
228 compatible = "fsl,imx8qxp-lpcg";
231 #clock-cells = <1>;
232 clock-indices = <IMX_LPCG_CLK_4>;
233 clock-output-names = "pi0_lpcg_ipg_clk";
234 power-domains = <&pd IMX_SC_R_ISI_CH0>;
237 pi0_pxl_lpcg: clock-controller@58263018 {
238 compatible = "fsl,imx8qxp-lpcg";
241 #clock-cells = <1>;
242 clock-indices = <IMX_LPCG_CLK_0>;
243 clock-output-names = "pi0_lpcg_pxl_clk";
244 power-domains = <&pd IMX_SC_R_ISI_CH0>;
247 pi0_misc_lpcg: clock-controller@5826301c {
248 compatible = "fsl,imx8qxp-lpcg";
251 #clock-cells = <1>;
252 clock-indices = <IMX_LPCG_CLK_0>;
253 clock-output-names = "pi0_lpcg_misc_clk";
254 power-domains = <&pd IMX_SC_R_ISI_CH0>;
258 compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
263 clock-names = "per", "ipg";
264 assigned-clocks = <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>;
265 assigned-clock-rates = <24000000>;
266 interrupt-parent = <&irqsteer_parallel>;
267 power-domains = <&pd IMX_SC_R_PI_0_I2C_0>;
276 assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
278 assigned-clock-rates = <200000000>, <200000000>;
279 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
288 assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
290 assigned-clock-rates = <200000000>, <200000000>;
291 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
295 pdma0_lpcg: clock-controller@58500000 {
296 compatible = "fsl,imx8qxp-lpcg";
299 #clock-cells = <1>;
300 clock-indices = <IMX_LPCG_CLK_0>;
301 clock-output-names = "pdma0_lpcg_clk";
302 power-domains = <&pd IMX_SC_R_ISI_CH0>;
305 pdma1_lpcg: clock-controller@58510000 {
306 compatible = "fsl,imx8qxp-lpcg";
309 #clock-cells = <1>;
310 clock-indices = <IMX_LPCG_CLK_0>;
311 clock-output-names = "pdma1_lpcg_clk";
312 power-domains = <&pd IMX_SC_R_ISI_CH1>;
315 pdma2_lpcg: clock-controller@58520000 {
316 compatible = "fsl,imx8qxp-lpcg";
319 #clock-cells = <1>;
320 clock-indices = <IMX_LPCG_CLK_0>;
321 clock-output-names = "pdma2_lpcg_clk";
322 power-domains = <&pd IMX_SC_R_ISI_CH2>;
325 pdma3_lpcg: clock-controller@58530000 {
326 compatible = "fsl,imx8qxp-lpcg";
329 #clock-cells = <1>;
330 clock-indices = <IMX_LPCG_CLK_0>;
331 clock-output-names = "pdma3_lpcg_clk";
332 power-domains = <&pd IMX_SC_R_ISI_CH3>;
335 pdma4_lpcg: clock-controller@58540000 {
336 compatible = "fsl,imx8qxp-lpcg";
339 #clock-cells = <1>;
340 clock-indices = <IMX_LPCG_CLK_0>;
341 clock-output-names = "pdma4_lpcg_clk";
342 power-domains = <&pd IMX_SC_R_ISI_CH4>;
345 pdma5_lpcg: clock-controller@58550000 {
346 compatible = "fsl,imx8qxp-lpcg";
349 #clock-cells = <1>;
350 clock-indices = <IMX_LPCG_CLK_0>;
351 clock-output-names = "pdma5_lpcg_clk";
352 power-domains = <&pd IMX_SC_R_ISI_CH5>;
355 pdma6_lpcg: clock-controller@58560000 {
356 compatible = "fsl,imx8qxp-lpcg";
359 #clock-cells = <1>;
360 clock-indices = <IMX_LPCG_CLK_0>;
361 clock-output-names = "pdma6_lpcg_clk";
362 power-domains = <&pd IMX_SC_R_ISI_CH6>;
365 pdma7_lpcg: clock-controller@58570000 {
366 compatible = "fsl,imx8qxp-lpcg";
369 #clock-cells = <1>;
370 clock-indices = <IMX_LPCG_CLK_0>;
371 clock-output-names = "pdma7_lpcg_clk";
372 power-domains = <&pd IMX_SC_R_ISI_CH7>;
375 csi0_pxl_lpcg: clock-controller@58580000 {
376 compatible = "fsl,imx8qxp-lpcg";
379 #clock-cells = <1>;
380 clock-indices = <IMX_LPCG_CLK_0>;
381 clock-output-names = "csi0_lpcg_pxl_clk";
382 power-domains = <&pd IMX_SC_R_CSI_0>;
385 csi1_pxl_lpcg: clock-controller@58590000 {
386 compatible = "fsl,imx8qxp-lpcg";
389 #clock-cells = <1>;
390 clock-indices = <IMX_LPCG_CLK_0>;
391 clock-output-names = "csi1_lpcg_pxl_clk";
392 power-domains = <&pd IMX_SC_R_CSI_1>;
395 hdmi_rx_pxl_link_lpcg: clock-controller@585a0000 {
396 compatible = "fsl,imx8qxp-lpcg";
399 #clock-cells = <1>;
400 clock-indices = <IMX_LPCG_CLK_0>;
401 clock-output-names = "hdmi_rx_lpcg_pxl_link_clk";
402 power-domains = <&pd IMX_SC_R_HDMI_RX>;
405 img_jpeg_dec_lpcg: clock-controller@585d0000 {
406 compatible = "fsl,imx8qxp-lpcg";
408 #clock-cells = <1>;
410 clock-indices = <IMX_LPCG_CLK_0>,
412 clock-output-names = "img_jpeg_dec_lpcg_clk",
414 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
417 img_jpeg_enc_lpcg: clock-controller@585f0000 {
418 compatible = "fsl,imx8qxp-lpcg";
420 #clock-cells = <1>;
422 clock-indices = <IMX_LPCG_CLK_0>,
424 clock-output-names = "img_jpeg_enc_lpcg_clk",
426 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;