Lines Matching +full:num +full:- +full:tx +full:- +full:queues
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 conn_axi_clk: clock-conn-axi {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <333333333>;
14 clock-output-names = "conn_axi_clk";
17 conn_ahb_clk: clock-conn-ahb {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <166666666>;
21 clock-output-names = "conn_ahb_clk";
24 conn_ipg_clk: clock-conn-ipg {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <83333333>;
28 clock-output-names = "conn_ipg_clk";
31 conn_bch_clk: clock-conn-bch {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <400000000>;
35 clock-output-names = "conn_bch_clk";
39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <1>;
45 compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb";
47 interrupt-parent = <&gic>;
52 ahb-burst-config = <0x0>;
53 tx-burst-size-dword = <0x10>;
54 rx-burst-size-dword = <0x10>;
55 power-domains = <&pd IMX_SC_R_USB_0>;
60 #index-cells = <1>;
61 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
66 compatible = "fsl,imx7ulp-usbphy";
69 power-domains = <&pd IMX_SC_R_USB_0_PHY>;
79 clock-names = "ipg", "ahb", "per";
80 assigned-clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>;
81 assigned-clock-rates = <400000000>;
82 power-domains = <&pd IMX_SC_R_SDHC_0>;
83 fsl,tuning-start-tap = <20>;
84 fsl,tuning-step = <2>;
94 clock-names = "ipg", "ahb", "per";
95 assigned-clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>;
96 assigned-clock-rates = <200000000>;
97 power-domains = <&pd IMX_SC_R_SDHC_1>;
98 fsl,tuning-start-tap = <20>;
99 fsl,tuning-step = <2>;
109 clock-names = "ipg", "ahb", "per";
110 assigned-clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>;
111 assigned-clock-rates = <200000000>;
112 power-domains = <&pd IMX_SC_R_SDHC_2>;
113 fsl,tuning-start-tap = <20>;
114 fsl,tuning-step = <2>;
129 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
130 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
132 assigned-clock-rates = <250000000>, <125000000>;
133 fsl,num-tx-queues = <3>;
134 fsl,num-rx-queues = <3>;
135 power-domains = <&pd IMX_SC_R_ENET_0>;
150 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp", "enet_2x_txclk";
151 assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
153 assigned-clock-rates = <250000000>, <125000000>;
154 fsl,num-tx-queues = <3>;
155 fsl,num-rx-queues = <3>;
156 power-domains = <&pd IMX_SC_R_ENET_1>;
161 compatible = "fsl,imx8qm-usb3";
163 #address-cells = <1>;
164 #size-cells = <1>;
171 clock-names = "lpm", "bus", "aclk", "ipg", "core";
172 assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
173 assigned-clock-rates = <250000000>;
174 power-domains = <&pd IMX_SC_R_USB_2>;
182 reg-names = "otg", "xhci", "dev";
183 interrupt-parent = <&gic>;
188 interrupt-names = "host", "peripheral", "otg", "wakeup";
190 phy-names = "cdns3,usb3-phy";
191 cdns,on-chip-buff-size = /bits/ 16 <18>;
196 usb3_phy: usb-phy@5b160000 {
197 compatible = "nxp,salvo-phy";
200 clock-names = "salvo_phy_clk";
201 power-domains = <&pd IMX_SC_R_USB_2_PHY>;
202 #phy-cells = <0>;
207 sdhc0_lpcg: clock-controller@5b200000 {
208 compatible = "fsl,imx8qxp-lpcg";
210 #clock-cells = <1>;
213 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
215 clock-output-names = "sdhc0_lpcg_per_clk",
218 power-domains = <&pd IMX_SC_R_SDHC_0>;
221 sdhc1_lpcg: clock-controller@5b210000 {
222 compatible = "fsl,imx8qxp-lpcg";
224 #clock-cells = <1>;
227 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
229 clock-output-names = "sdhc1_lpcg_per_clk",
232 power-domains = <&pd IMX_SC_R_SDHC_1>;
235 sdhc2_lpcg: clock-controller@5b220000 {
236 compatible = "fsl,imx8qxp-lpcg";
238 #clock-cells = <1>;
241 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
243 clock-output-names = "sdhc2_lpcg_per_clk",
246 power-domains = <&pd IMX_SC_R_SDHC_2>;
249 enet0_lpcg: clock-controller@5b230000 {
250 compatible = "fsl,imx8qxp-lpcg";
252 #clock-cells = <1>;
259 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
262 clock-output-names = "enet0_lpcg_timer_clk",
268 power-domains = <&pd IMX_SC_R_ENET_0>;
271 enet1_lpcg: clock-controller@5b240000 {
272 compatible = "fsl,imx8qxp-lpcg";
274 #clock-cells = <1>;
281 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
284 clock-output-names = "enet1_lpcg_timer_clk",
290 power-domains = <&pd IMX_SC_R_ENET_1>;
293 usb2_lpcg: clock-controller@5b270000 {
294 compatible = "fsl,imx8qxp-lpcg";
296 #clock-cells = <1>;
298 clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
299 clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
300 power-domains = <&pd IMX_SC_R_USB_0_PHY>;
303 usb3_lpcg: clock-controller@5b280000 {
304 compatible = "fsl,imx8qxp-lpcg";
306 #clock-cells = <1>;
307 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
316 clock-output-names = "usb3_app_clk",
322 power-domains = <&pd IMX_SC_R_USB_2_PHY>;
325 rawnand_0_lpcg: clock-controller@5b290000 {
326 compatible = "fsl,imx8qxp-lpcg";
328 #clock-cells = <1>;
333 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
335 clock-output-names = "gpmi_bch",
339 power-domains = <&pd IMX_SC_R_NAND>;
342 rawnand_4_lpcg: clock-controller@5b290004 {
343 compatible = "fsl,imx8qxp-lpcg";
345 #clock-cells = <1>;
347 clock-indices = <IMX_LPCG_CLK_4>;
348 clock-output-names = "apbhdma_hclk";
349 power-domains = <&pd IMX_SC_R_NAND>;
352 dma_apbh: dma-controller@5b810000 {
353 compatible = "fsl,imx8qxp-dma-apbh", "fsl,imx28-dma-apbh";
359 #dma-cells = <1>;
360 dma-channels = <4>;
362 power-domains = <&pd IMX_SC_R_NAND>;
365 gpmi: nand-controller@5b812000 {
366 compatible = "fsl,imx8qxp-gpmi-nand";
368 reg-names = "gpmi-nand", "bch";
369 #address-cells = <1>;
370 #size-cells = <0>;
372 interrupt-names = "bch";
377 clock-names = "gpmi_io", "gpmi_apb",
380 dma-names = "rx-tx";
381 power-domains = <&pd IMX_SC_R_NAND>;
382 assigned-clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>;
383 assigned-clock-rates = <50000000>;