Lines Matching +full:imx8qxp +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
10 conn_axi_clk: clock-conn-axi {
11 compatible = "fixed-clock";
12 #clock-cells = <0>;
13 clock-frequency = <333333333>;
14 clock-output-names = "conn_axi_clk";
17 conn_ahb_clk: clock-conn-ahb {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <166666666>;
21 clock-output-names = "conn_ahb_clk";
24 conn_ipg_clk: clock-conn-ipg {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <83333333>;
28 clock-output-names = "conn_ipg_clk";
31 conn_bch_clk: clock-conn-bch {
32 compatible = "fixed-clock";
33 #clock-cells = <0>;
34 clock-frequency = <400000000>;
35 clock-output-names = "conn_bch_clk";
39 compatible = "simple-bus";
40 #address-cells = <1>;
41 #size-cells = <1>;
45 compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb";
47 interrupt-parent = <&gic>;
52 ahb-burst-config = <0x0>;
53 tx-burst-size-dword = <0x10>;
54 rx-burst-size-dword = <0x10>;
55 power-domains = <&pd IMX_SC_R_USB_0>;
60 #index-cells = <1>;
61 compatible = "fsl,imx7ulp-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc";
66 compatible = "fsl,imx7ulp-usbphy";
69 power-domains = <&pd IMX_SC_R_USB_0_PHY>;
79 clock-names = "ipg", "ahb", "per";
80 power-domains = <&pd IMX_SC_R_SDHC_0>;
90 clock-names = "ipg", "ahb", "per";
91 power-domains = <&pd IMX_SC_R_SDHC_1>;
92 fsl,tuning-start-tap = <20>;
93 fsl,tuning-step = <2>;
103 clock-names = "ipg", "ahb", "per";
104 power-domains = <&pd IMX_SC_R_SDHC_2>;
118 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
119 assigned-clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
120 <&clk IMX_SC_R_ENET_0 IMX_SC_C_CLKDIV>;
121 assigned-clock-rates = <250000000>, <125000000>;
122 fsl,num-tx-queues = <3>;
123 fsl,num-rx-queues = <3>;
124 power-domains = <&pd IMX_SC_R_ENET_0>;
138 clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
139 assigned-clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
140 <&clk IMX_SC_R_ENET_1 IMX_SC_C_CLKDIV>;
141 assigned-clock-rates = <250000000>, <125000000>;
142 fsl,num-tx-queues = <3>;
143 fsl,num-rx-queues = <3>;
144 power-domains = <&pd IMX_SC_R_ENET_1>;
149 compatible = "fsl,imx8qm-usb3";
151 #address-cells = <1>;
152 #size-cells = <1>;
159 clock-names = "lpm", "bus", "aclk", "ipg", "core";
160 assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
161 assigned-clock-rates = <250000000>;
162 power-domains = <&pd IMX_SC_R_USB_2>;
170 reg-names = "otg", "xhci", "dev";
171 interrupt-parent = <&gic>;
176 interrupt-names = "host", "peripheral", "otg", "wakeup";
178 phy-names = "cdns3,usb3-phy";
179 cdns,on-chip-buff-size = /bits/ 16 <18>;
184 usb3_phy: usb-phy@5b160000 {
185 compatible = "nxp,salvo-phy";
188 clock-names = "salvo_phy_clk";
189 power-domains = <&pd IMX_SC_R_USB_2_PHY>;
190 #phy-cells = <0>;
195 sdhc0_lpcg: clock-controller@5b200000 {
196 compatible = "fsl,imx8qxp-lpcg";
198 #clock-cells = <1>;
199 clocks = <&clk IMX_SC_R_SDHC_0 IMX_SC_PM_CLK_PER>,
201 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
203 clock-output-names = "sdhc0_lpcg_per_clk",
206 power-domains = <&pd IMX_SC_R_SDHC_0>;
209 sdhc1_lpcg: clock-controller@5b210000 {
210 compatible = "fsl,imx8qxp-lpcg";
212 #clock-cells = <1>;
213 clocks = <&clk IMX_SC_R_SDHC_1 IMX_SC_PM_CLK_PER>,
215 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
217 clock-output-names = "sdhc1_lpcg_per_clk",
220 power-domains = <&pd IMX_SC_R_SDHC_1>;
223 sdhc2_lpcg: clock-controller@5b220000 {
224 compatible = "fsl,imx8qxp-lpcg";
226 #clock-cells = <1>;
227 clocks = <&clk IMX_SC_R_SDHC_2 IMX_SC_PM_CLK_PER>,
229 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
231 clock-output-names = "sdhc2_lpcg_per_clk",
234 power-domains = <&pd IMX_SC_R_SDHC_2>;
237 enet0_lpcg: clock-controller@5b230000 {
238 compatible = "fsl,imx8qxp-lpcg";
240 #clock-cells = <1>;
241 clocks = <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
242 <&clk IMX_SC_R_ENET_0 IMX_SC_PM_CLK_PER>,
244 <&clk IMX_SC_R_ENET_0 IMX_SC_C_TXCLK>,
247 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
250 clock-output-names = "enet0_lpcg_timer_clk",
256 power-domains = <&pd IMX_SC_R_ENET_0>;
259 enet1_lpcg: clock-controller@5b240000 {
260 compatible = "fsl,imx8qxp-lpcg";
262 #clock-cells = <1>;
263 clocks = <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
264 <&clk IMX_SC_R_ENET_1 IMX_SC_PM_CLK_PER>,
266 <&clk IMX_SC_R_ENET_1 IMX_SC_C_TXCLK>,
269 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
272 clock-output-names = "enet1_lpcg_timer_clk",
278 power-domains = <&pd IMX_SC_R_ENET_1>;
281 usb2_lpcg: clock-controller@5b270000 {
282 compatible = "fsl,imx8qxp-lpcg";
284 #clock-cells = <1>;
286 clock-indices = <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
287 clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
288 power-domains = <&pd IMX_SC_R_USB_0_PHY>;
291 usb3_lpcg: clock-controller@5b280000 {
292 compatible = "fsl,imx8qxp-lpcg";
294 #clock-cells = <1>;
295 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
298 clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
299 <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
303 <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
304 clock-output-names = "usb3_app_clk",
310 power-domains = <&pd IMX_SC_R_USB_2_PHY>;
313 rawnand_0_lpcg: clock-controller@5b290000 {
314 compatible = "fsl,imx8qxp-lpcg";
316 #clock-cells = <1>;
317 clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_PER>,
318 <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>,
321 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
323 clock-output-names = "gpmi_bch",
327 power-domains = <&pd IMX_SC_R_NAND>;
330 rawnand_4_lpcg: clock-controller@5b290004 {
331 compatible = "fsl,imx8qxp-lpcg";
333 #clock-cells = <1>;
335 clock-indices = <IMX_LPCG_CLK_4>;
336 clock-output-names = "apbhdma_hclk";
337 power-domains = <&pd IMX_SC_R_NAND>;
340 dma_apbh: dma-controller@5b810000 {
341 compatible = "fsl,imx8qxp-dma-apbh", "fsl,imx28-dma-apbh";
347 #dma-cells = <1>;
348 dma-channels = <4>;
350 power-domains = <&pd IMX_SC_R_NAND>;
353 gpmi: nand-controller@5b812000{
354 compatible = "fsl,imx8qxp-gpmi-nand";
356 reg-names = "gpmi-nand", "bch";
357 #address-cells = <1>;
358 #size-cells = <0>;
360 interrupt-names = "bch";
365 clock-names = "gpmi_io", "gpmi_apb",
368 dma-names = "rx-tx";
369 power-domains = <&pd IMX_SC_R_NAND>;
370 assigned-clocks = <&clk IMX_SC_R_NAND IMX_SC_PM_CLK_MST_BUS>;
371 assigned-clock-rates = <50000000>;