Lines Matching +full:0 +full:x5b160000
12 #clock-cells = <0>;
19 #clock-cells = <0>;
26 #clock-cells = <0>;
33 #clock-cells = <0>;
42 ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
46 reg = <0x5b0d0000 0x200>;
50 fsl,usbmisc = <&usbmisc1 0>;
52 ahb-burst-config = <0x0>;
53 tx-burst-size-dword = <0x10>;
54 rx-burst-size-dword = <0x10>;
62 reg = <0x5b0d0200 0x200>;
67 reg = <0x5b100000 0x1000>;
75 reg = <0x5b010000 0x10000>;
86 reg = <0x5b020000 0x10000>;
99 reg = <0x5b030000 0x10000>;
109 reg = <0x5b040000 0x10000>;
129 reg = <0x5b050000 0x10000>;
150 reg = <0x5b110000 0x10000>;
167 reg = <0x5b120000 0x10000>, /* memory area for OTG/DRD registers */
168 <0x5b130000 0x10000>, /* memory area for HOST registers */
169 <0x5b140000 0x10000>; /* memory area for DEVICE registers */
186 reg = <0x5b160000 0x40000>;
190 #phy-cells = <0>;
197 reg = <0x5b200000 0x10000>;
211 reg = <0x5b210000 0x10000>;
225 reg = <0x5b220000 0x10000>;
239 reg = <0x5b230000 0x10000>;
261 reg = <0x5b240000 0x10000>;
283 reg = <0x5b270000 0x10000>;
293 reg = <0x5b280000 0x10000>;
315 reg = <0x5b290000 0x4>;
332 reg = <0x5b290004 0x10000>;
342 reg = <0x5b810000 0x2000>;
355 reg = <0x5b812000 0x2000>, <0x5b814000 0x2000>;
358 #size-cells = <0>;
367 dmas = <&dma_apbh 0>;