Lines Matching +full:clock +full:- +full:indices
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
7 #include <dt-bindings/clock/imx8-clock.h>
8 #include <dt-bindings/clock/imx8-lpcg.h>
9 #include <dt-bindings/dma/fsl-edma.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
12 audio_ipg_clk: clock-audio-ipg {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <120000000>;
16 clock-output-names = "audio_ipg_clk";
19 clk_ext_aud_mclk0: clock-ext-aud-mclk0 {
20 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <0>;
23 clock-output-names = "ext_aud_mclk0";
26 clk_ext_aud_mclk1: clock-ext-aud-mclk1 {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <0>;
30 clock-output-names = "ext_aud_mclk1";
33 clk_esai0_rx_clk: clock-esai0-rx {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <0>;
37 clock-output-names = "esai0_rx_clk";
40 clk_esai0_rx_hf_clk: clock-esai0-rx-hf {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <0>;
44 clock-output-names = "esai0_rx_hf_clk";
47 clk_esai0_tx_clk: clock-esai0-tx {
48 compatible = "fixed-clock";
49 #clock-cells = <0>;
50 clock-frequency = <0>;
51 clock-output-names = "esai0_tx_clk";
54 clk_esai0_tx_hf_clk: clock-esai0-tx-hf {
55 compatible = "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <0>;
58 clock-output-names = "esai0_tx_hf_clk";
61 clk_spdif0_rx: clock-spdif0-rx {
62 compatible = "fixed-clock";
63 #clock-cells = <0>;
64 clock-frequency = <0>;
65 clock-output-names = "spdif0_rx";
68 clk_sai0_rx_bclk: clock-sai0-rx-bclk {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <0>;
72 clock-output-names = "sai0_rx_bclk";
75 clk_sai0_tx_bclk: clock-sai0-tx-bclk {
76 compatible = "fixed-clock";
77 #clock-cells = <0>;
78 clock-frequency = <0>;
79 clock-output-names = "sai0_tx_bclk";
82 clk_sai1_rx_bclk: clock-sai1-rx-bclk {
83 compatible = "fixed-clock";
84 #clock-cells = <0>;
85 clock-frequency = <0>;
86 clock-output-names = "sai1_rx_bclk";
89 clk_sai1_tx_bclk: clock-sai1-tx-bclk {
90 compatible = "fixed-clock";
91 #clock-cells = <0>;
92 clock-frequency = <0>;
93 clock-output-names = "sai1_tx_bclk";
96 clk_sai2_rx_bclk: clock-sai2-rx-bclk {
97 compatible = "fixed-clock";
98 #clock-cells = <0>;
99 clock-frequency = <0>;
100 clock-output-names = "sai2_rx_bclk";
103 clk_sai3_rx_bclk: clock-sai3-rx-bclk {
104 compatible = "fixed-clock";
105 #clock-cells = <0>;
106 clock-frequency = <0>;
107 clock-output-names = "sai3_rx_bclk";
110 clk_sai4_rx_bclk: clock-sai4-rx-bclk {
111 compatible = "fixed-clock";
112 #clock-cells = <0>;
113 clock-frequency = <0>;
114 clock-output-names = "sai4_rx_bclk";
118 compatible = "simple-bus";
119 #address-cells = <1>;
120 #size-cells = <1>;
124 compatible = "fsl,imx8qm-asrc";
146 clock-names = "mem", "ipg",
159 dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
160 fsl,asrc-rate = <8000>;
161 fsl,asrc-width = <16>;
162 fsl,asrc-clk-map = <0>;
163 power-domains = <&pd IMX_SC_R_ASRC_0>;
168 compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai";
175 clock-names = "core", "extal", "fsys", "spba";
177 dma-names = "rx", "tx";
178 power-domains = <&pd IMX_SC_R_ESAI_0>;
183 compatible = "fsl,imx8qm-spdif";
197 clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4",
201 dma-names = "rx", "tx";
202 power-domains = <&pd IMX_SC_R_SPDIF_0>;
207 compatible = "fsl,imx8qm-sai";
215 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
216 dma-names = "rx", "tx";
218 power-domains = <&pd IMX_SC_R_SAI_0>;
223 compatible = "fsl,imx8qm-sai";
231 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
232 dma-names = "rx", "tx";
234 power-domains = <&pd IMX_SC_R_SAI_1>;
239 compatible = "fsl,imx8qm-sai";
247 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
248 dma-names = "rx";
250 power-domains = <&pd IMX_SC_R_SAI_2>;
255 compatible = "fsl,imx8qm-sai";
263 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
264 dma-names = "rx";
266 power-domains = <&pd IMX_SC_R_SAI_3>;
270 edma0: dma-controller@591f0000 {
271 compatible = "fsl,imx8qm-edma";
273 #dma-cells = <3>;
274 dma-channels = <24>;
275 dma-channel-mask = <0x5c0c00>;
300 power-domains = <&pd IMX_SC_R_DMA_0_CH0>,
326 asrc0_lpcg: clock-controller@59400000 {
327 compatible = "fsl,imx8qxp-lpcg";
329 #clock-cells = <1>;
331 clock-indices = <IMX_LPCG_CLK_4>;
332 clock-output-names = "asrc0_lpcg_ipg_clk";
333 power-domains = <&pd IMX_SC_R_ASRC_0>;
336 esai0_lpcg: clock-controller@59410000 {
337 compatible = "fsl,imx8qxp-lpcg";
339 #clock-cells = <1>;
342 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
343 clock-output-names = "esai0_lpcg_extal_clk",
345 power-domains = <&pd IMX_SC_R_ESAI_0>;
348 spdif0_lpcg: clock-controller@59420000 {
349 compatible = "fsl,imx8qxp-lpcg";
351 #clock-cells = <1>;
354 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
355 clock-output-names = "spdif0_lpcg_tx_clk",
357 power-domains = <&pd IMX_SC_R_SPDIF_0>;
360 sai0_lpcg: clock-controller@59440000 {
361 compatible = "fsl,imx8qxp-lpcg";
363 #clock-cells = <1>;
366 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
367 clock-output-names = "sai0_lpcg_mclk",
369 power-domains = <&pd IMX_SC_R_SAI_0>;
372 sai1_lpcg: clock-controller@59450000 {
373 compatible = "fsl,imx8qxp-lpcg";
375 #clock-cells = <1>;
378 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
379 clock-output-names = "sai1_lpcg_mclk",
381 power-domains = <&pd IMX_SC_R_SAI_1>;
384 sai2_lpcg: clock-controller@59460000 {
385 compatible = "fsl,imx8qxp-lpcg";
387 #clock-cells = <1>;
390 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
391 clock-output-names = "sai2_lpcg_mclk",
393 power-domains = <&pd IMX_SC_R_SAI_2>;
396 sai3_lpcg: clock-controller@59470000 {
397 compatible = "fsl,imx8qxp-lpcg";
399 #clock-cells = <1>;
402 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
403 clock-output-names = "sai3_lpcg_mclk",
405 power-domains = <&pd IMX_SC_R_SAI_3>;
408 dsp_lpcg: clock-controller@59580000 {
409 compatible = "fsl,imx8qxp-lpcg";
411 #clock-cells = <1>;
415 clock-indices = <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
417 clock-output-names = "dsp_lpcg_adb_clk",
420 power-domains = <&pd IMX_SC_R_DSP>;
423 dsp_ram_lpcg: clock-controller@59590000 {
424 compatible = "fsl,imx8qxp-lpcg";
426 #clock-cells = <1>;
428 clock-indices = <IMX_LPCG_CLK_4>;
429 clock-output-names = "dsp_ram_lpcg_ipg_clk";
430 power-domains = <&pd IMX_SC_R_DSP_RAM>;
434 compatible = "fsl,imx8qxp-hifi4";
439 clock-names = "ipg", "ocram", "core";
440 power-domains = <&pd IMX_SC_R_MU_13B>,
442 mbox-names = "tx", "rx", "rxdb";
446 firmware-name = "imx/dsp/hifi4.bin";
451 compatible = "fsl,imx8qm-asrc";
473 clock-names = "mem", "ipg",
486 dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc";
487 fsl,asrc-rate = <8000>;
488 fsl,asrc-width = <16>;
489 fsl,asrc-clk-map = <1>;
490 power-domains = <&pd IMX_SC_R_ASRC_1>;
495 compatible = "fsl,imx8qm-sai";
503 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
505 dma-names = "rx", "tx";
506 power-domains = <&pd IMX_SC_R_SAI_4>;
511 compatible = "fsl,imx8qm-sai";
519 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
521 dma-names = "tx";
522 power-domains = <&pd IMX_SC_R_SAI_5>;
527 compatible = "fsl,imx8qm-audmix";
530 clock-names = "ipg";
531 power-domains = <&pd IMX_SC_R_AMIX>;
537 compatible = "fsl,imx8qm-mqs";
540 clock-names = "mclk", "core";
541 power-domains = <&pd IMX_SC_R_MQS_0>;
545 edma1: dma-controller@599f0000 {
546 compatible = "fsl,imx8qm-edma";
548 #dma-cells = <3>;
549 dma-channels = <11>;
550 dma-channel-mask = <0xc0>;
562 power-domains = <&pd IMX_SC_R_DMA_1_CH0>,
575 aud_rec0_lpcg: clock-controller@59d00000 {
576 compatible = "fsl,imx8qxp-lpcg";
578 #clock-cells = <1>;
580 clock-indices = <IMX_LPCG_CLK_0>;
581 clock-output-names = "aud_rec_clk0_lpcg_clk";
582 power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>;
585 aud_rec1_lpcg: clock-controller@59d10000 {
586 compatible = "fsl,imx8qxp-lpcg";
588 #clock-cells = <1>;
590 clock-indices = <IMX_LPCG_CLK_0>;
591 clock-output-names = "aud_rec_clk1_lpcg_clk";
592 power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>;
595 aud_pll_div0_lpcg: clock-controller@59d20000 {
596 compatible = "fsl,imx8qxp-lpcg";
598 #clock-cells = <1>;
600 clock-indices = <IMX_LPCG_CLK_0>;
601 clock-output-names = "aud_pll_div_clk0_lpcg_clk";
602 power-domains = <&pd IMX_SC_R_AUDIO_PLL_0>;
605 aud_pll_div1_lpcg: clock-controller@59d30000 {
606 compatible = "fsl,imx8qxp-lpcg";
608 #clock-cells = <1>;
610 clock-indices = <IMX_LPCG_CLK_0>;
611 clock-output-names = "aud_pll_div_clk1_lpcg_clk";
612 power-domains = <&pd IMX_SC_R_AUDIO_PLL_1>;
615 mclkout0_lpcg: clock-controller@59d50000 {
616 compatible = "fsl,imx8qxp-lpcg";
618 #clock-cells = <1>;
620 clock-indices = <IMX_LPCG_CLK_0>;
621 clock-output-names = "mclkout0_lpcg_clk";
622 power-domains = <&pd IMX_SC_R_MCLK_OUT_0>;
625 mclkout1_lpcg: clock-controller@59d60000 {
626 compatible = "fsl,imx8qxp-lpcg";
628 #clock-cells = <1>;
630 clock-indices = <IMX_LPCG_CLK_0>;
631 clock-output-names = "mclkout1_lpcg_clk";
632 power-domains = <&pd IMX_SC_R_MCLK_OUT_1>;
636 compatible = "fsl,imx8qxp-acm";
638 #clock-cells = <1>;
639 power-domains = <&pd IMX_SC_R_AUDIO_CLK_0>,
674 clock-names = "aud_rec_clk0_lpcg_clk",
694 asrc1_lpcg: clock-controller@59c00000 {
695 compatible = "fsl,imx8qxp-lpcg";
697 #clock-cells = <1>;
699 clock-indices = <IMX_LPCG_CLK_4>;
700 clock-output-names = "asrc1_lpcg_ipg_clk";
701 power-domains = <&pd IMX_SC_R_ASRC_1>;
704 sai4_lpcg: clock-controller@59c20000 {
705 compatible = "fsl,imx8qxp-lpcg";
707 #clock-cells = <1>;
710 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
711 clock-output-names = "sai4_lpcg_mclk",
713 power-domains = <&pd IMX_SC_R_SAI_4>;
716 sai5_lpcg: clock-controller@59c30000 {
717 compatible = "fsl,imx8qxp-lpcg";
719 #clock-cells = <1>;
722 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
723 clock-output-names = "sai5_lpcg_mclk",
725 power-domains = <&pd IMX_SC_R_SAI_5>;
728 amix_lpcg: clock-controller@59c40000 {
729 compatible = "fsl,imx8qxp-lpcg";
731 #clock-cells = <1>;
733 clock-indices = <IMX_LPCG_CLK_0>;
734 clock-output-names = "amix_lpcg_ipg_clk";
735 power-domains = <&pd IMX_SC_R_AMIX>;
738 mqs0_lpcg: clock-controller@59c50000 {
739 compatible = "fsl,imx8qxp-lpcg";
741 #clock-cells = <1>;
744 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
745 clock-output-names = "mqs0_lpcg_mclk",
747 power-domains = <&pd IMX_SC_R_MQS_0>;