Lines Matching +full:0 +full:x59850000
14 #clock-cells = <0>;
21 #clock-cells = <0>;
22 clock-frequency = <0>;
28 #clock-cells = <0>;
29 clock-frequency = <0>;
35 #clock-cells = <0>;
36 clock-frequency = <0>;
42 #clock-cells = <0>;
43 clock-frequency = <0>;
49 #clock-cells = <0>;
50 clock-frequency = <0>;
56 #clock-cells = <0>;
57 clock-frequency = <0>;
63 #clock-cells = <0>;
64 clock-frequency = <0>;
70 #clock-cells = <0>;
71 clock-frequency = <0>;
77 #clock-cells = <0>;
78 clock-frequency = <0>;
84 #clock-cells = <0>;
85 clock-frequency = <0>;
91 #clock-cells = <0>;
92 clock-frequency = <0>;
98 #clock-cells = <0>;
99 clock-frequency = <0>;
105 #clock-cells = <0>;
106 clock-frequency = <0>;
112 #clock-cells = <0>;
113 clock-frequency = <0>;
121 ranges = <0x59000000 0x0 0x59000000 0x1000000>;
125 reg = <0x59000000 0x10000>;
152 dmas = <&edma0 0 0 0>,
153 <&edma0 1 0 0>,
154 <&edma0 2 0 0>,
155 <&edma0 3 0 FSL_EDMA_RX>,
156 <&edma0 4 0 FSL_EDMA_RX>,
157 <&edma0 5 0 FSL_EDMA_RX>;
162 fsl,asrc-clk-map = <0>;
169 reg = <0x59010000 0x10000>;
176 dmas = <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>;
184 reg = <0x59020000 0x10000>;
199 dmas = <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>,
200 <&edma0 9 0 FSL_EDMA_MULTI_FIFO>;
208 reg = <0x59040000 0x10000>;
217 dmas = <&edma0 12 0 1>, <&edma0 13 0 0>;
224 reg = <0x59050000 0x10000>;
233 dmas = <&edma0 14 0 1>, <&edma0 15 0 0>;
240 reg = <0x59060000 0x10000>;
249 dmas = <&edma0 16 0 1>;
256 reg = <0x59070000 0x10000>;
265 dmas = <&edma0 17 0 1>;
272 reg = <0x591f0000 0x190000>;
275 dma-channel-mask = <0x5c0c00>;
276 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 0 */
286 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 10 unused */
287 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 11 unused */
294 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 18 unused */
295 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 19 unused */
296 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 20 unused */
298 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 22 unused */
328 reg = <0x59400000 0x10000>;
338 reg = <0x59410000 0x10000>;
350 reg = <0x59420000 0x10000>;
362 reg = <0x59440000 0x10000>;
374 reg = <0x59450000 0x10000>;
386 reg = <0x59460000 0x10000>;
398 reg = <0x59470000 0x10000>;
410 reg = <0x59580000 0x10000>;
425 reg = <0x59590000 0x10000>;
435 reg = <0x596e8000 0x88000>;
443 mboxes = <&lsio_mu13 0 0>,
444 <&lsio_mu13 1 0>,
445 <&lsio_mu13 3 0>;
452 reg = <0x59800000 0x10000>;
479 dmas = <&edma1 0 0 0>,
480 <&edma1 1 0 0>,
481 <&edma1 2 0 0>,
482 <&edma1 3 0 FSL_EDMA_RX>,
483 <&edma1 4 0 FSL_EDMA_RX>,
484 <&edma1 5 0 FSL_EDMA_RX>;
496 reg = <0x59820000 0x10000>;
504 dmas = <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>;
512 reg = <0x59830000 0x10000>;
520 dmas = <&edma1 10 0 0>;
528 reg = <0x59840000 0x10000>;
538 reg = <0x59850000 0x10000>;
547 reg = <0x599f0000 0xc0000>;
550 dma-channel-mask = <0xc0>;
551 interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 1 */
557 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 6 unused */
558 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 7 unused */
577 reg = <0x59d00000 0x10000>;
587 reg = <0x59d10000 0x10000>;
597 reg = <0x59d20000 0x10000>;
607 reg = <0x59d30000 0x10000>;
617 reg = <0x59d50000 0x10000>;
627 reg = <0x59d60000 0x10000>;
637 reg = <0x59e00000 0x1d0000>;
696 reg = <0x59c00000 0x10000>;
706 reg = <0x59c20000 0x10000>;
718 reg = <0x59c30000 0x10000>;
730 reg = <0x59c40000 0x10000>;
740 reg = <0x59c50000 0x10000>;