Lines Matching +full:0 +full:x54
35 mux-controls = <&mux 0>;
38 #size-cells = <0>;
40 mdio@0 { /* On-board RTL8211F PHY #1 RGMII1 */
41 reg = <0x00>;
43 #size-cells = <0>;
47 reg = <0x1>;
53 reg = <0x8>;
55 #size-cells = <0>;
59 reg = <0x2>;
65 reg = <0x18>;
67 #size-cells = <0>;
71 reg = <0x19>;
73 #size-cells = <0>;
77 reg = <0x1a>;
79 #size-cells = <0>;
83 reg = <0x1b>;
85 #size-cells = <0>;
89 reg = <0x1c>;
91 #size-cells = <0>;
95 reg = <0x1d>;
97 #size-cells = <0>;
101 reg = <0x1e>;
103 #size-cells = <0>;
107 reg = <0x1f>;
109 #size-cells = <0>;
118 #size-cells = <0>;
120 mdio@0 { /* Slot #1 (secondary EMI) */
121 reg = <0x00>;
123 #size-cells = <0>;
127 reg = <0x01>;
129 #size-cells = <0>;
133 reg = <0x02>;
135 #size-cells = <0>;
139 reg = <0x03>;
141 #size-cells = <0>;
145 reg = <0x04>;
147 #size-cells = <0>;
151 reg = <0x05>;
153 #size-cells = <0>;
157 reg = <0x06>;
159 #size-cells = <0>;
163 reg = <0x07>;
165 #size-cells = <0>;
195 dflash0: flash@0 {
199 reg = <0>;
207 dflash1: flash@0 {
211 reg = <0>;
219 dflash2: flash@0 {
223 reg = <0>;
254 mt35xu512aba0: flash@0 {
260 reg = <0>;
272 reg = <0x66>;
277 mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
278 <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */
284 reg = <0x77>;
286 #size-cells = <0>;
290 #size-cells = <0>;
291 reg = <0x2>;
295 reg = <0x40>;
301 reg = <0x41>;
308 #size-cells = <0>;
309 reg = <0x3>;
313 reg = <0x4c>;
319 reg = <0x51>;