Lines Matching +full:0 +full:x1e30
12 /memreserve/ 0x80000000 0x00010000;
26 #size-cells = <0>;
29 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
35 d-cache-size = <0x8000>;
38 i-cache-size = <0xC000>;
50 reg = <0x1>;
51 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
52 d-cache-size = <0x8000>;
55 i-cache-size = <0xC000>;
67 reg = <0x100>;
69 d-cache-size = <0x8000>;
72 i-cache-size = <0xC000>;
84 reg = <0x101>;
86 d-cache-size = <0x8000>;
89 i-cache-size = <0xC000>;
101 reg = <0x200>;
103 d-cache-size = <0x8000>;
106 i-cache-size = <0xC000>;
118 reg = <0x201>;
120 d-cache-size = <0x8000>;
123 i-cache-size = <0xC000>;
135 reg = <0x300>;
137 d-cache-size = <0x8000>;
140 i-cache-size = <0xC000>;
152 reg = <0x301>;
154 d-cache-size = <0x8000>;
157 i-cache-size = <0xC000>;
169 reg = <0x400>;
171 d-cache-size = <0x8000>;
174 i-cache-size = <0xC000>;
186 reg = <0x401>;
188 d-cache-size = <0x8000>;
191 i-cache-size = <0xC000>;
203 reg = <0x500>;
205 d-cache-size = <0x8000>;
208 i-cache-size = <0xC000>;
220 reg = <0x501>;
222 d-cache-size = <0x8000>;
225 i-cache-size = <0xC000>;
237 reg = <0x600>;
239 d-cache-size = <0x8000>;
242 i-cache-size = <0xC000>;
254 reg = <0x601>;
256 d-cache-size = <0x8000>;
259 i-cache-size = <0xC000>;
271 reg = <0x700>;
273 d-cache-size = <0x8000>;
276 i-cache-size = <0xC000>;
288 reg = <0x701>;
290 d-cache-size = <0x8000>;
293 i-cache-size = <0xC000>;
304 cache-size = <0x100000>;
313 cache-size = <0x100000>;
322 cache-size = <0x100000>;
331 cache-size = <0x100000>;
340 cache-size = <0x100000>;
349 cache-size = <0x100000>;
358 cache-size = <0x100000>;
367 cache-size = <0x100000>;
376 arm,psci-suspend-param = <0x0>;
385 reg = <0x0 0x06000000 0 0x10000>, // GIC Dist
386 <0x0 0x06200000 0 0x200000>, // GICR (RD_base +
388 <0x0 0x0c0c0000 0 0x2000>, // GICC
389 <0x0 0x0c0d0000 0 0x1000>, // GICH
390 <0x0 0x0c0e0000 0 0x20000>; // GICV
402 reg = <0x0 0x6020000 0 0x20000>;
427 reg = <0x00000000 0x80000000 0 0x80000000>;
432 reg = <0x0 0x1080000 0x0 0x1000>;
439 reg = <0x0 0x1090000 0x0 0x1000>;
447 #clock-cells = <0>;
456 thermal-sensors = <&tmu 0>;
622 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
626 reg = <0x0 0x1ea0000 0x0 0x1e30>;
632 reg = <0x0 0x1eb0000 0x0 0x1e30>;
638 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
642 ranges = <0x0 0x00 0x8000000 0x100000>;
643 reg = <0x00 0x8000000 0x0 0x100000>;
649 compatible = "fsl,sec-v5.0-job-ring",
650 "fsl,sec-v4.0-job-ring";
651 reg = <0x10000 0x10000>;
656 compatible = "fsl,sec-v5.0-job-ring",
657 "fsl,sec-v4.0-job-ring";
658 reg = <0x20000 0x10000>;
663 compatible = "fsl,sec-v5.0-job-ring",
664 "fsl,sec-v4.0-job-ring";
665 reg = <0x30000 0x10000>;
670 compatible = "fsl,sec-v5.0-job-ring",
671 "fsl,sec-v4.0-job-ring";
672 reg = <0x40000 0x10000>;
679 reg = <0 0x1300000 0 0xa0000>;
686 reg = <0x0 0x1e00000 0x0 0x10000>;
692 reg = <0x0 0x1e80000 0x0 0x10000>;
700 reg = <0x0 0x1f70000 0x0 0x10000>;
704 ranges = <0x0 0x0 0x1f70000 0x10000>;
709 #address-cells = <0>;
711 reg = <0x14 4>;
713 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
714 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
715 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
716 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
717 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
718 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
719 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
720 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
721 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
722 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
723 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
724 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
725 interrupt-map-mask = <0xf 0x0>;
731 reg = <0x0 0x1f80000 0x0 0x10000>;
733 fsl,tmu-range = <0x800000e6 0x8001017d>;
736 <0x00000000 0x00000035>,
738 <0x00000001 0x00000154>;
746 #size-cells = <0>;
747 reg = <0x0 0x2000000 0x0 0x10000>;
753 pinctrl-0 = <&i2c0_scl>;
762 #size-cells = <0>;
763 reg = <0x0 0x2010000 0x0 0x10000>;
769 pinctrl-0 = <&i2c1_scl>;
778 #size-cells = <0>;
779 reg = <0x0 0x2020000 0x0 0x10000>;
785 pinctrl-0 = <&i2c2_scl>;
794 #size-cells = <0>;
795 reg = <0x0 0x2030000 0x0 0x10000>;
801 pinctrl-0 = <&i2c3_scl>;
810 #size-cells = <0>;
811 reg = <0x0 0x2040000 0x0 0x10000>;
817 pinctrl-0 = <&i2c4_scl>;
826 #size-cells = <0>;
827 reg = <0x0 0x2050000 0x0 0x10000>;
833 pinctrl-0 = <&i2c5_scl>;
842 #size-cells = <0>;
843 reg = <0x0 0x2060000 0x0 0x10000>;
849 pinctrl-0 = <&i2c6_scl>;
858 #size-cells = <0>;
859 reg = <0x0 0x2070000 0x0 0x10000>;
865 pinctrl-0 = <&i2c7_scl>;
874 #size-cells = <0>;
875 reg = <0x0 0x20c0000 0x0 0x10000>,
876 <0x0 0x20000000 0x0 0x10000000>;
890 #size-cells = <0>;
891 reg = <0x0 0x2100000 0x0 0x10000>;
897 bus-num = <0>;
904 #size-cells = <0>;
905 reg = <0x0 0x2110000 0x0 0x10000>;
918 #size-cells = <0>;
919 reg = <0x0 0x2120000 0x0 0x10000>;
931 reg = <0x0 0x2140000 0x0 0x10000>;
945 reg = <0x0 0x2150000 0x0 0x10000>;
960 reg = <0x0 0x2180000 0x0 0x10000>;
964 <&clockgen QORIQ_CLK_SYSCLK 0>;
966 fsl,clk-source = /bits/ 8 <0>;
972 reg = <0x0 0x2190000 0x0 0x10000>;
976 <&clockgen QORIQ_CLK_SYSCLK 0>;
978 fsl,clk-source = /bits/ 8 <0>;
989 reg = <0x0 0x21c0000 0x0 0x1000>;
1001 reg = <0x0 0x21d0000 0x0 0x1000>;
1013 reg = <0x0 0x21e0000 0x0 0x1000>;
1025 reg = <0x0 0x21f0000 0x0 0x1000>;
1032 reg = <0x0 0x2300000 0x0 0x10000>;
1043 reg = <0x0 0x2310000 0x0 0x10000>;
1054 reg = <0x0 0x2320000 0x0 0x10000>;
1065 reg = <0x0 0x2330000 0x0 0x10000>;
1076 reg = <0x0 0x23a0000 0 0x1000>,
1077 <0x0 0x2390000 0 0x1000>;
1084 reg = <0x0 0x1e34040 0x0 0x1c>;
1091 reg = <0x0 0x2800000 0x0 0x10000>;
1092 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
1098 reg = <0x0 0x3100000 0x0 0x10000>;
1101 snps,quirk-frame-length-adjustment = <0x20>;
1110 reg = <0x0 0x3110000 0x0 0x10000>;
1113 snps,quirk-frame-length-adjustment = <0x20>;
1122 reg = <0x0 0x3200000 0x0 0x10000>,
1123 <0x7 0x100520 0x0 0x4>;
1134 reg = <0x0 0x3210000 0x0 0x10000>,
1135 <0x7 0x100520 0x0 0x4>;
1146 reg = <0x0 0x3220000 0x0 0x10000>,
1147 <0x7 0x100520 0x0 0x4>;
1158 reg = <0x0 0x3230000 0x0 0x10000>,
1159 <0x7 0x100520 0x0 0x4>;
1170 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
1171 <0x80 0x00000000 0x0 0x00002000>; /* configuration space */
1183 bus-range = <0x0 0xff>;
1184 … ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1185 msi-parent = <&its 0>;
1187 interrupt-map-mask = <0 0 0 7>;
1188 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1189 <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1190 <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
1191 <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
1192 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1198 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
1199 <0x88 0x00000000 0x0 0x00002000>; /* configuration space */
1211 bus-range = <0x0 0xff>;
1212 … ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1213 msi-parent = <&its 0>;
1215 interrupt-map-mask = <0 0 0 7>;
1216 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
1217 <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
1218 <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1219 <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1220 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1226 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
1227 <0x90 0x00000000 0x0 0x00002000>; /* configuration space */
1239 bus-range = <0x0 0xff>;
1240 … ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1241 msi-parent = <&its 0>;
1243 interrupt-map-mask = <0 0 0 7>;
1244 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1245 <0000 0 0 2 &gic 0 0 GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1246 <0000 0 0 3 &gic 0 0 GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
1247 <0000 0 0 4 &gic 0 0 GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1248 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1254 reg = <0x00 0x03700000 0x0 0x00100000>, /* controller registers */
1255 <0x98 0x00000000 0x0 0x00002000>; /* configuration space */
1267 bus-range = <0x0 0xff>;
1268 … ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1269 msi-parent = <&its 0>;
1271 interrupt-map-mask = <0 0 0 7>;
1272 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1273 <0000 0 0 2 &gic 0 0 GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1274 <0000 0 0 3 &gic 0 0 GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1275 <0000 0 0 4 &gic 0 0 GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1276 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1282 reg = <0x00 0x03800000 0x0 0x00100000>, /* controller registers */
1283 <0xa0 0x00000000 0x0 0x00002000>; /* configuration space */
1295 bus-range = <0x0 0xff>;
1296 … ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1297 msi-parent = <&its 0>;
1299 interrupt-map-mask = <0 0 0 7>;
1300 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1301 <0000 0 0 2 &gic 0 0 GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1302 <0000 0 0 3 &gic 0 0 GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1303 <0000 0 0 4 &gic 0 0 GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
1304 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1310 reg = <0x00 0x03900000 0x0 0x00100000>, /* controller registers */
1311 <0xa8 0x00000000 0x0 0x00002000>; /* configuration space */
1323 bus-range = <0x0 0xff>;
1324 … ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
1325 msi-parent = <&its 0>;
1327 interrupt-map-mask = <0 0 0 7>;
1328 interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1329 <0000 0 0 2 &gic 0 0 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1330 <0000 0 0 3 &gic 0 0 GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1331 <0000 0 0 4 &gic 0 0 GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1332 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1338 reg = <0 0x5000000 0 0x800000>;
1349 // performance counter interrupts 0-9
1430 reg = <0x00000000 0x08340020 0 0x2>;
1435 reg = <0x0 0x8b95000 0x0 0x100>;
1442 /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
1445 reg = <0x0 0x8b96000 0x0 0x1000>;
1448 #size-cells = <0>;
1458 reg = <0x0 0x8b97000 0x0 0x1000>;
1462 #size-cells = <0>;
1471 reg = <0x0 0x8c07000 0x0 0x1000>;
1474 #size-cells = <0>;
1477 pcs1: ethernet-phy@0 {
1478 reg = <0>;
1484 reg = <0x0 0x8c0b000 0x0 0x1000>;
1487 #size-cells = <0>;
1490 pcs2: ethernet-phy@0 {
1491 reg = <0>;
1497 reg = <0x0 0x8c0f000 0x0 0x1000>;
1500 #size-cells = <0>;
1503 pcs3: ethernet-phy@0 {
1504 reg = <0>;
1510 reg = <0x0 0x8c13000 0x0 0x1000>;
1513 #size-cells = <0>;
1516 pcs4: ethernet-phy@0 {
1517 reg = <0>;
1523 reg = <0x0 0x8c17000 0x0 0x1000>;
1526 #size-cells = <0>;
1529 pcs5: ethernet-phy@0 {
1530 reg = <0>;
1536 reg = <0x0 0x8c1b000 0x0 0x1000>;
1539 #size-cells = <0>;
1542 pcs6: ethernet-phy@0 {
1543 reg = <0>;
1549 reg = <0x0 0x8c1f000 0x0 0x1000>;
1552 #size-cells = <0>;
1555 pcs7: ethernet-phy@0 {
1556 reg = <0>;
1562 reg = <0x0 0x8c23000 0x0 0x1000>;
1565 #size-cells = <0>;
1568 pcs8: ethernet-phy@0 {
1569 reg = <0>;
1575 reg = <0x0 0x8c27000 0x0 0x1000>;
1578 #size-cells = <0>;
1581 pcs9: ethernet-phy@0 {
1582 reg = <0>;
1588 reg = <0x0 0x8c2b000 0x0 0x1000>;
1591 #size-cells = <0>;
1594 pcs10: ethernet-phy@0 {
1595 reg = <0>;
1601 reg = <0x0 0x8c2f000 0x0 0x1000>;
1604 #size-cells = <0>;
1607 pcs11: ethernet-phy@0 {
1608 reg = <0>;
1614 reg = <0x0 0x8c33000 0x0 0x1000>;
1617 #size-cells = <0>;
1620 pcs12: ethernet-phy@0 {
1621 reg = <0>;
1627 reg = <0x0 0x8c37000 0x0 0x1000>;
1630 #size-cells = <0>;
1633 pcs13: ethernet-phy@0 {
1634 reg = <0>;
1640 reg = <0x0 0x8c3b000 0x0 0x1000>;
1643 #size-cells = <0>;
1646 pcs14: ethernet-phy@0 {
1647 reg = <0>;
1653 reg = <0x0 0x8c3f000 0x0 0x1000>;
1656 #size-cells = <0>;
1659 pcs15: ethernet-phy@0 {
1660 reg = <0>;
1666 reg = <0x0 0x8c43000 0x0 0x1000>;
1669 #size-cells = <0>;
1672 pcs16: ethernet-phy@0 {
1673 reg = <0>;
1679 reg = <0x0 0x8c47000 0x0 0x1000>;
1682 #size-cells = <0>;
1685 pcs17: ethernet-phy@0 {
1686 reg = <0>;
1692 reg = <0x0 0x8c4b000 0x0 0x1000>;
1695 #size-cells = <0>;
1698 pcs18: ethernet-phy@0 {
1699 reg = <0>;
1705 reg = <0x00000007 0x0010012c 0x0 0xc>;
1707 #size-cells = <0>;
1710 pinctrl-single,function-mask = <0x7>;
1713 pinctrl-single,bits = <0x0 0 0x7>;
1717 pinctrl-single,bits = <0x0 0x1 0x7>;
1721 pinctrl-single,bits = <0x0 0 (0x7 << 3)>;
1725 pinctrl-single,bits = <0x0 (0x1 << 3) (0x7 << 3)>;
1729 pinctrl-single,bits = <0x0 0 (0x7 << 6)>;
1733 pinctrl-single,bits = <0x0 (0x1 << 6) (0x7 << 6)>;
1737 pinctrl-single,bits = <0x0 0 (0x7 << 9)>;
1741 pinctrl-single,bits = <0x0 (0x1 << 9) (0x7 << 9)>;
1745 pinctrl-single,bits = <0x0 0 (0x7 << 12)>;
1749 pinctrl-single,bits = <0x0 (0x1 << 12) (0x7 << 12)>;
1753 pinctrl-single,bits = <0x4 0x2 0x7>;
1757 pinctrl-single,bits = <0x4 0x1 0x7>;
1761 pinctrl-single,bits = <0x4 0x2 0x7>;
1765 pinctrl-single,bits = <0x4 0x1 0x7>;
1769 pinctrl-single,bits = <0x8 0 (0x7 << 10)>;
1773 pinctrl-single,bits = <0x8 (0x1 << 10) (0x7 << 10)>;
1779 reg = <0x00000008 0x0c000000 0 0x40>,
1780 <0x00000000 0x08340000 0 0x40000>;
1781 msi-parent = <&its 0>;
1783 iommu-map = <0 &smmu 0 0>;
1789 * Region type 0x0 - MC portals
1790 * Region type 0x1 - QBMAN portals
1792 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
1793 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
1800 #size-cells = <0>;
1804 reg = <0x1>;
1810 reg = <0x2>;
1816 reg = <0x3>;
1822 reg = <0x4>;
1828 reg = <0x5>;
1834 reg = <0x6>;
1840 reg = <0x7>;
1846 reg = <0x8>;
1852 reg = <0x9>;
1858 reg = <0xa>;
1864 reg = <0xb>;
1870 reg = <0xc>;
1876 reg = <0xd>;
1882 reg = <0xe>;
1888 reg = <0xf>;
1894 reg = <0x10>;
1900 reg = <0x11>;
1906 reg = <0x12>;