Lines Matching +full:0 +full:x54
37 mux-controls = <&mux 0>;
40 #size-cells = <0>;
42 mdio@0 { /* On-board PHY #1 RGMI1*/
43 reg = <0x00>;
45 #size-cells = <0>;
49 reg = <0x8>;
51 #size-cells = <0>;
55 reg = <0x18>;
57 #size-cells = <0>;
61 reg = <0x19>;
63 #size-cells = <0>;
67 reg = <0x1a>;
69 #size-cells = <0>;
73 reg = <0x1b>;
75 #size-cells = <0>;
79 reg = <0x1c>;
81 #size-cells = <0>;
85 reg = <0x1d>;
87 #size-cells = <0>;
91 reg = <0x1e>;
93 #size-cells = <0>;
97 reg = <0x1f>;
99 #size-cells = <0>;
108 #size-cells = <0>;
110 mdio@0 { /* Slot #1 (secondary EMI) */
111 reg = <0x00>;
113 #size-cells = <0>;
117 reg = <0x01>;
119 #size-cells = <0>;
123 reg = <0x02>;
125 #size-cells = <0>;
129 reg = <0x03>;
131 #size-cells = <0>;
135 reg = <0x04>;
137 #size-cells = <0>;
141 reg = <0x05>;
143 #size-cells = <0>;
147 reg = <0x06>;
149 #size-cells = <0>;
153 reg = <0x07>;
155 #size-cells = <0>;
175 dflash0: flash@0 {
179 reg = <0>;
187 dflash1: flash@0 {
191 reg = <0>;
199 dflash2: flash@0 {
203 reg = <0>;
227 mt35xu512aba0: flash@0 {
233 reg = <0>;
245 reg = <0x66>;
250 mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
251 <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */
257 reg = <0x77>;
259 #size-cells = <0>;
263 #size-cells = <0>;
264 reg = <0x2>;
268 reg = <0x40>;
274 reg = <0x41>;
281 #size-cells = <0>;
282 reg = <0x3>;
286 reg = <0x4c>;
292 reg = <0x4d>;
298 reg = <0x51>;