Lines Matching +full:0 +full:x00030001
33 #size-cells = <0>;
38 reg = <0x00000000 0x80000000 0 0x80000000>;
44 #clock-cells = <0>;
51 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
53 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
54 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
55 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
67 reg = <0x0 0x6020000 0 0x20000>;
73 reg = <0x0 0x1e60000 0x0 0x4>;
77 offset = <0x0>;
78 mask = <0x2>;
260 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
264 reg = <0 0x1300000 0 0xa0000>;
271 reg = <0x0 0x1e00000 0x0 0x10000>;
277 reg = <0x0 0x1e80000 0x0 0x10000>;
285 reg = <0x0 0x1f70000 0x0 0x10000>;
289 ranges = <0x0 0x0 0x1f70000 0x10000>;
294 #address-cells = <0>;
296 reg = <0x14 4>;
298 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
299 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
300 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
301 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
302 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
303 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
304 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
305 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
306 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
307 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
308 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
309 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
310 interrupt-map-mask = <0xf 0x0>;
316 reg = <0x0 0x1f80000 0x0 0x10000>;
318 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
320 <0x00000000 0x00000026>,
321 <0x00000001 0x0000002d>,
322 <0x00000002 0x00000032>,
323 <0x00000003 0x00000039>,
324 <0x00000004 0x0000003f>,
325 <0x00000005 0x00000046>,
326 <0x00000006 0x0000004d>,
327 <0x00000007 0x00000054>,
328 <0x00000008 0x0000005a>,
329 <0x00000009 0x00000061>,
330 <0x0000000a 0x0000006a>,
331 <0x0000000b 0x00000071>,
333 <0x00010000 0x00000025>,
334 <0x00010001 0x0000002c>,
335 <0x00010002 0x00000035>,
336 <0x00010003 0x0000003d>,
337 <0x00010004 0x00000045>,
338 <0x00010005 0x0000004e>,
339 <0x00010006 0x00000057>,
340 <0x00010007 0x00000061>,
341 <0x00010008 0x0000006b>,
342 <0x00010009 0x00000076>,
344 <0x00020000 0x00000029>,
345 <0x00020001 0x00000033>,
346 <0x00020002 0x0000003d>,
347 <0x00020003 0x00000049>,
348 <0x00020004 0x00000056>,
349 <0x00020005 0x00000061>,
350 <0x00020006 0x0000006d>,
352 <0x00030000 0x00000021>,
353 <0x00030001 0x0000002a>,
354 <0x00030002 0x0000003c>,
355 <0x00030003 0x0000004e>;
362 reg = <0x0 0x21c0500 0x0 0x100>;
370 reg = <0x0 0x21c0600 0x0 0x100>;
378 reg = <0x0 0x21d0500 0x0 0x100>;
386 reg = <0x0 0x21d0600 0x0 0x100>;
394 reg = <0x0 0xc000000 0x0 0x1000>;
404 reg = <0x0 0xc010000 0x0 0x1000>;
414 reg = <0x0 0xc100000 0x0 0x1000>;
424 reg = <0x0 0xc110000 0x0 0x1000>;
434 reg = <0x0 0xc200000 0x0 0x1000>;
444 reg = <0x0 0xc210000 0x0 0x1000>;
454 reg = <0x0 0xc300000 0x0 0x1000>;
464 reg = <0x0 0xc310000 0x0 0x1000>;
473 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
477 ranges = <0x0 0x00 0x8000000 0x100000>;
478 reg = <0x00 0x8000000 0x0 0x100000>;
483 compatible = "fsl,sec-v5.0-job-ring",
484 "fsl,sec-v4.0-job-ring";
485 reg = <0x10000 0x10000>;
490 compatible = "fsl,sec-v5.0-job-ring",
491 "fsl,sec-v4.0-job-ring";
492 reg = <0x20000 0x10000>;
497 compatible = "fsl,sec-v5.0-job-ring",
498 "fsl,sec-v4.0-job-ring";
499 reg = <0x30000 0x10000>;
504 compatible = "fsl,sec-v5.0-job-ring",
505 "fsl,sec-v4.0-job-ring";
506 reg = <0x40000 0x10000>;
513 reg = <0x00000000 0x08340020 0 0x2>;
518 reg = <0x0 0x8b95000 0x0 0x100>;
527 reg = <0x0 0x8b96000 0x0 0x1000>;
530 #size-cells = <0>;
539 reg = <0x0 0x8b97000 0x0 0x1000>;
542 #size-cells = <0>;
551 reg = <0x0 0x8c07000 0x0 0x1000>;
554 #size-cells = <0>;
557 pcs1: ethernet-phy@0 {
558 reg = <0>;
564 reg = <0x0 0x8c0b000 0x0 0x1000>;
567 #size-cells = <0>;
570 pcs2: ethernet-phy@0 {
571 reg = <0>;
577 reg = <0x0 0x8c0f000 0x0 0x1000>;
580 #size-cells = <0>;
583 pcs3: ethernet-phy@0 {
584 reg = <0>;
590 reg = <0x0 0x8c13000 0x0 0x1000>;
593 #size-cells = <0>;
596 pcs4: ethernet-phy@0 {
597 reg = <0>;
603 reg = <0x0 0x8c17000 0x0 0x1000>;
606 #size-cells = <0>;
609 pcs5: ethernet-phy@0 {
610 reg = <0>;
616 reg = <0x0 0x8c1b000 0x0 0x1000>;
619 #size-cells = <0>;
622 pcs6: ethernet-phy@0 {
623 reg = <0>;
629 reg = <0x0 0x8c1f000 0x0 0x1000>;
632 #size-cells = <0>;
635 pcs7: ethernet-phy@0 {
636 reg = <0>;
642 reg = <0x0 0x8c23000 0x0 0x1000>;
645 #size-cells = <0>;
648 pcs8: ethernet-phy@0 {
649 reg = <0>;
655 reg = <0x0 0x8c27000 0x0 0x1000>;
658 #size-cells = <0>;
661 pcs9: ethernet-phy@0 {
662 reg = <0>;
668 reg = <0x0 0x8c2b000 0x0 0x1000>;
671 #size-cells = <0>;
674 pcs10: ethernet-phy@0 {
675 reg = <0>;
681 reg = <0x0 0x8c2f000 0x0 0x1000>;
684 #size-cells = <0>;
687 pcs11: ethernet-phy@0 {
688 reg = <0>;
694 reg = <0x0 0x8c33000 0x0 0x1000>;
697 #size-cells = <0>;
700 pcs12: ethernet-phy@0 {
701 reg = <0>;
707 reg = <0x0 0x8c37000 0x0 0x1000>;
710 #size-cells = <0>;
713 pcs13: ethernet-phy@0 {
714 reg = <0>;
720 reg = <0x0 0x8c3b000 0x0 0x1000>;
723 #size-cells = <0>;
726 pcs14: ethernet-phy@0 {
727 reg = <0>;
733 reg = <0x0 0x8c3f000 0x0 0x1000>;
736 #size-cells = <0>;
739 pcs15: ethernet-phy@0 {
740 reg = <0>;
746 reg = <0x0 0x8c43000 0x0 0x1000>;
749 #size-cells = <0>;
752 pcs16: ethernet-phy@0 {
753 reg = <0>;
759 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
760 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
761 msi-parent = <&its 0>;
762 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
768 * Region type 0x0 - MC portals
769 * Region type 0x1 - QBMAN portals
771 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
772 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
779 #size-cells = <0>;
783 reg = <0x1>;
789 reg = <0x2>;
795 reg = <0x3>;
801 reg = <0x4>;
807 reg = <0x5>;
813 reg = <0x6>;
819 reg = <0x7>;
825 reg = <0x8>;
831 reg = <0x9>;
837 reg = <0xa>;
843 reg = <0xb>;
849 reg = <0xc>;
855 reg = <0xd>;
861 reg = <0xe>;
867 reg = <0xf>;
873 reg = <0x10>;
881 reg = <0 0x5000000 0 0x800000>;
884 stream-match-mask = <0x7C00>;
890 /* performance counter interrupts 0-7 */
934 #size-cells = <0>;
935 reg = <0x0 0x2100000 0x0 0x10000>;
946 reg = <0x0 0x2140000 0x0 0x10000>;
958 reg = <0x0 0x2300000 0x0 0x10000>;
969 reg = <0x0 0x2310000 0x0 0x10000>;
980 reg = <0x0 0x2320000 0x0 0x10000>;
991 reg = <0x0 0x2330000 0x0 0x10000>;
1004 #size-cells = <0>;
1005 reg = <0x0 0x2000000 0x0 0x10000>;
1016 #size-cells = <0>;
1017 reg = <0x0 0x2010000 0x0 0x10000>;
1028 #size-cells = <0>;
1029 reg = <0x0 0x2020000 0x0 0x10000>;
1040 #size-cells = <0>;
1041 reg = <0x0 0x2030000 0x0 0x10000>;
1050 reg = <0x0 0x2240000 0x0 0x20000>;
1056 ranges = <0 0 0x5 0x80000000 0x08000000
1057 2 0 0x5 0x30000000 0x00010000
1058 3 0 0x5 0x20000000 0x00010000>;
1064 #size-cells = <0>;
1065 reg = <0x0 0x20c0000 0x0 0x10000>,
1066 <0x0 0x20000000 0x0 0x10000000>;
1087 bus-range = <0x0 0xff>;
1088 msi-parent = <&its 0>;
1090 interrupt-map-mask = <0 0 0 7>;
1091 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
1092 <0000 0 0 2 &gic 0 0 0 110 4>,
1093 <0000 0 0 3 &gic 0 0 0 111 4>,
1094 <0000 0 0 4 &gic 0 0 0 112 4>;
1095 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1109 bus-range = <0x0 0xff>;
1110 msi-parent = <&its 0>;
1112 interrupt-map-mask = <0 0 0 7>;
1113 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
1114 <0000 0 0 2 &gic 0 0 0 115 4>,
1115 <0000 0 0 3 &gic 0 0 0 116 4>,
1116 <0000 0 0 4 &gic 0 0 0 117 4>;
1117 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1131 bus-range = <0x0 0xff>;
1132 msi-parent = <&its 0>;
1134 interrupt-map-mask = <0 0 0 7>;
1135 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
1136 <0000 0 0 2 &gic 0 0 0 120 4>,
1137 <0000 0 0 3 &gic 0 0 0 121 4>,
1138 <0000 0 0 4 &gic 0 0 0 122 4>;
1139 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1153 bus-range = <0x0 0xff>;
1154 msi-parent = <&its 0>;
1156 interrupt-map-mask = <0 0 0 7>;
1157 interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
1158 <0000 0 0 2 &gic 0 0 0 125 4>,
1159 <0000 0 0 3 &gic 0 0 0 126 4>,
1160 <0000 0 0 4 &gic 0 0 0 127 4>;
1161 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
1168 reg = <0x0 0x3200000 0x0 0x10000>;
1178 reg = <0x0 0x3210000 0x0 0x10000>;
1190 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
1194 reg = <0x0 0x3100000 0x0 0x10000>;
1197 snps,quirk-frame-length-adjustment = <0x20>;
1205 reg = <0x0 0x3110000 0x0 0x10000>;
1208 snps,quirk-frame-length-adjustment = <0x20>;
1217 reg = <0x0 0x04000000 0x0 0x01000000>;
1223 reg = <0x0 0x1e34040 0x0 0x18>;
1230 reg = <0x0 0x2800000 0x0 0x10000>;
1231 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
1238 reg = <0x0 0x1080000 0x0 0x1000>;
1245 reg = <0x0 0x1090000 0x0 0x1000>;