Lines Matching +full:mdio +full:- +full:mux +full:- +full:1
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 phy-handle = <&mdio0_phy12>;
15 phy-connection-type = "sgmii";
19 phy-handle = <&mdio0_phy13>;
20 phy-connection-type = "sgmii";
24 phy-handle = <&mdio0_phy14>;
25 phy-connection-type = "sgmii";
29 phy-handle = <&mdio0_phy15>;
30 phy-connection-type = "sgmii";
34 mmc-hs200-1_8v;
40 #address-cells = <2>;
41 #size-cells = <1>;
47 #address-cells = <1>;
48 #size-cells = <1>;
49 compatible = "cfi-flash";
51 bank-width = <2>;
52 device-width = <1>;
56 compatible = "fsl,ifc-nand";
60 boardctrl: board-control@3,0 {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 compatible = "fsl,ls208xaqds-fpga", "fsl,fpga-qixis", "simple-mfd";
67 mdio-mux@54 {
68 compatible = "mdio-mux-mmioreg", "mdio-mux";
69 mdio-parent-bus = <&emdio1>;
70 reg = <0x54 1>; /* BRDCFG4 */
71 mux-mask = <0xe0>; /* EMI1_MDIO */
72 #address-cells = <1>;
73 #size-cells = <0>;
75 /* Child MDIO buses, one for each riser card:
79 mdio_mux3: mdio@60 {
81 #address-cells = <1>;
82 #size-cells = <0>;
84 mdio0_phy12: mdio-phy0@1c {
88 mdio0_phy13: mdio-phy1@1d {
92 mdio0_phy14: mdio-phy2@1e {
96 mdio0_phy15: mdio-phy3@1f {
106 i2c-mux@77 {
109 #address-cells = <1>;
110 #size-cells = <0>;
112 #address-cells = <1>;
113 #size-cells = <0>;
122 #address-cells = <1>;
123 #size-cells = <0>;
129 shunt-resistor = <500>;
135 shunt-resistor = <1000>;
140 #address-cells = <1>;
141 #size-cells = <0>;
167 #address-cells = <1>;
168 #size-cells = <1>;
170 spi-max-frequency = <3000000>;
173 dflash1: flash@1 {
174 #address-cells = <1>;
175 #size-cells = <1>;
177 spi-max-frequency = <3000000>;
178 reg = <1>;
181 #address-cells = <1>;
182 #size-cells = <1>;
184 spi-max-frequency = <3000000>;
192 #address-cells = <1>;
193 #size-cells = <1>;
195 spi-max-frequency = <20000000>;
196 spi-rx-bus-width = <4>;
197 spi-tx-bus-width = <4>;
201 #address-cells = <1>;
202 #size-cells = <1>;
204 spi-max-frequency = <20000000>;
205 spi-rx-bus-width = <4>;
206 spi-tx-bus-width = <4>;