Lines Matching +full:0 +full:x0000003a
27 #size-cells = <0>;
30 cpu0: cpu@0 {
33 reg = <0x0>;
34 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
42 reg = <0x1>;
43 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
51 reg = <0x2>;
52 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
60 reg = <0x3>;
61 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
69 reg = <0x100>;
78 reg = <0x101>;
87 reg = <0x102>;
96 reg = <0x103>;
105 arm,psci-suspend-param = <0x0>;
116 reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
117 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
118 <0x0 0x0c0c0000 0 0x2000>, /* GICC */
119 <0x0 0x0c0d0000 0 0x1000>, /* GICH */
120 <0x0 0x0c0e0000 0 0x20000>; /* GICV */
130 reg = <0x0 0x6020000 0 0x20000>;
138 thermal-sensors = <&tmu 0>;
205 #clock-cells = <0>;
213 offset = <0x0>;
214 mask = <0x02>;
222 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
226 reg = <0 0x1300000 0 0xa0000>;
233 reg = <0x0 0x1e00000 0x0 0x10000>;
239 reg = <0x0 0x1e60000 0x0 0x10000>;
244 reg = <0x0 0x1f70000 0x0 0x10000>;
248 ranges = <0x0 0x0 0x1f70000 0x10000>;
253 #address-cells = <0>;
255 reg = <0x14 4>;
257 <0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
258 <1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
259 <2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
260 <3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
261 <4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
262 <5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
263 <6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
264 <7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
265 <8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
266 <9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
267 <10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
268 <11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
269 interrupt-map-mask = <0xf 0x0>;
275 reg = <0x0 0x1e80000 0x0 0x10000>;
283 reg = <0x0 0x1f80000 0x0 0x10000>;
285 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
288 <0x00000000 0x00000023>,
289 <0x00000001 0x0000002a>,
290 <0x00000002 0x00000030>,
291 <0x00000003 0x00000037>,
292 <0x00000004 0x0000003d>,
293 <0x00000005 0x00000044>,
294 <0x00000006 0x0000004a>,
295 <0x00000007 0x00000051>,
296 <0x00000008 0x00000057>,
297 <0x00000009 0x0000005e>,
298 <0x0000000a 0x00000064>,
299 <0x0000000b 0x0000006b>,
301 <0x00010000 0x00000022>,
302 <0x00010001 0x0000002a>,
303 <0x00010002 0x00000032>,
304 <0x00010003 0x0000003a>,
305 <0x00010004 0x00000042>,
306 <0x00010005 0x0000004a>,
307 <0x00010006 0x00000052>,
308 <0x00010007 0x0000005a>,
309 <0x00010008 0x00000062>,
310 <0x00010009 0x0000006a>,
312 <0x00020000 0x00000021>,
313 <0x00020001 0x0000002b>,
314 <0x00020002 0x00000035>,
315 <0x00020003 0x00000040>,
316 <0x00020004 0x0000004a>,
317 <0x00020005 0x00000054>,
318 <0x00020006 0x0000005e>,
320 <0x00030000 0x00000010>,
321 <0x00030001 0x0000001c>,
322 <0x00030002 0x00000027>,
323 <0x00030003 0x00000032>,
324 <0x00030004 0x0000003e>,
325 <0x00030005 0x00000049>,
326 <0x00030006 0x00000054>,
327 <0x00030007 0x00000060>;
334 "fsl,ls1021a-v1.0-dspi";
336 #size-cells = <0>;
337 reg = <0x0 0x2100000 0x0 0x10000>;
348 reg = <0x0 0x21c0500 0x0 0x100>;
357 reg = <0x0 0x21c0600 0x0 0x100>;
366 reg = <0x0 0x2300000 0x0 0x10000>;
377 reg = <0x0 0x2310000 0x0 0x10000>;
388 reg = <0x0 0x2320000 0x0 0x10000>;
399 reg = <0x0 0x2330000 0x0 0x10000>;
410 reg = <0x0 0x2240000 0x0 0x20000>;
421 #size-cells = <0>;
422 reg = <0x0 0x2000000 0x0 0x10000>;
432 #size-cells = <0>;
433 reg = <0x0 0x2010000 0x0 0x10000>;
443 #size-cells = <0>;
444 reg = <0x0 0x2020000 0x0 0x10000>;
454 #size-cells = <0>;
455 reg = <0x0 0x2030000 0x0 0x10000>;
465 #size-cells = <0>;
466 reg = <0x0 0x20c0000 0x0 0x10000>,
467 <0x0 0x20000000 0x0 0x10000000>;
480 reg = <0x0 0x2140000 0x0 0x10000>;
482 clock-frequency = <0>;
493 reg = <0x0 0x3100000 0x0 0x10000>;
496 snps,quirk-frame-length-adjustment = <0x20>;
504 reg = <0x0 0x3110000 0x0 0x10000>;
507 snps,quirk-frame-length-adjustment = <0x20>;
515 reg = <0x0 0x3200000 0x0 0x10000>,
516 <0x7 0x100520 0x0 0x4>;
526 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
530 ranges = <0x0 0x00 0x8000000 0x100000>;
531 reg = <0x00 0x8000000 0x0 0x100000>;
536 compatible = "fsl,sec-v5.0-job-ring",
537 "fsl,sec-v4.0-job-ring";
538 reg = <0x10000 0x10000>;
543 compatible = "fsl,sec-v5.0-job-ring",
544 "fsl,sec-v4.0-job-ring";
545 reg = <0x20000 0x10000>;
550 compatible = "fsl,sec-v5.0-job-ring",
551 "fsl,sec-v4.0-job-ring";
552 reg = <0x30000 0x10000>;
557 compatible = "fsl,sec-v5.0-job-ring",
558 "fsl,sec-v4.0-job-ring";
559 reg = <0x40000 0x10000>;
566 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
567 <0x20 0x00000000 0x0 0x00002000>; /* configuration space */
576 bus-range = <0x0 0xff>;
577 ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */
578 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
579 msi-parent = <&its 0>;
581 interrupt-map-mask = <0 0 0 7>;
582 interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>,
583 <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>,
584 <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>,
585 <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>;
586 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
592 reg = <0x00 0x03400000 0x0 0x00100000>,
593 <0x20 0x00000000 0x8 0x00000000>;
605 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
606 <0x28 0x00000000 0x0 0x00002000>; /* configuration space */
615 bus-range = <0x0 0xff>;
616 ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */
617 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
618 msi-parent = <&its 0>;
620 interrupt-map-mask = <0 0 0 7>;
621 interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>,
622 <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>,
623 <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>,
624 <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>;
625 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
631 reg = <0x00 0x03500000 0x0 0x00100000>,
632 <0x28 0x00000000 0x8 0x00000000>;
643 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
644 <0x30 0x00000000 0x0 0x00002000>; /* configuration space */
653 bus-range = <0x0 0xff>;
654 ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */
655 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
656 msi-parent = <&its 0>;
658 interrupt-map-mask = <0 0 0 7>;
659 interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>,
660 <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>,
661 <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
662 <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
663 iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
669 reg = <0x00 0x03600000 0x0 0x00100000>,
670 <0x30 0x00000000 0x8 0x00000000>;
681 reg = <0 0x5000000 0 0x800000>;
683 stream-match-mask = <0x7C00>;
694 // performance counter interrupts 0-7
772 reg = <0x00000000 0x08340020 0 0x2>;
777 reg = <0x0 0x8b95000 0x0 0x100>;
786 reg = <0x0 0x8b96000 0x0 0x1000>;
789 #size-cells = <0>;
798 reg = <0x0 0x8b97000 0x0 0x1000>;
801 #size-cells = <0>;
810 reg = <0x0 0x8c07000 0x0 0x1000>;
813 #size-cells = <0>;
816 pcs1: ethernet-phy@0 {
817 reg = <0>;
823 reg = <0x0 0x8c0b000 0x0 0x1000>;
826 #size-cells = <0>;
829 pcs2: ethernet-phy@0 {
830 reg = <0>;
836 reg = <0x0 0x8c0f000 0x0 0x1000>;
839 #size-cells = <0>;
842 pcs3_0: ethernet-phy@0 {
843 reg = <0>;
861 reg = <0x0 0x8c1f000 0x0 0x1000>;
864 #size-cells = <0>;
867 pcs7_0: ethernet-phy@0 {
868 reg = <0>;
886 reg = <0x0 0xc000000 0x0 0x1000>;
896 reg = <0x0 0xc010000 0x0 0x1000>;
906 reg = <0x0 0xc020000 0x0 0x1000>;
916 reg = <0x0 0xc030000 0x0 0x1000>;
926 reg = <0x0 0xc100000 0x0 0x1000>;
936 reg = <0x0 0xc110000 0x0 0x1000>;
946 reg = <0x0 0xc120000 0x0 0x1000>;
956 reg = <0x0 0xc130000 0x0 0x1000>;
966 reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
967 <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
968 msi-parent = <&its 0>;
969 iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
975 * Region type 0x0 - MC portals
976 * Region type 0x1 - QBMAN portals
978 ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
979 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
983 #size-cells = <0>;
1032 reg = <0xa>;
1039 reg = <0x0 0x1e34040 0x0 0x18>;
1046 reg = <0x0 0x2800000 0x0 0x10000>;
1047 fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;