Lines Matching +full:10 +full:gbase +full:- +full:r
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
4 * Based on fsl-ls1088a-rdb.dts
5 * Copyright 2017-2020 NXP
6 * Copyright 2019-2021 Traverse Technologies
11 /dts-v1/;
13 #include "fsl-ls1088a.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/input/input.h>
28 stdout-path = "serial0:115200n8";
32 compatible = "gpio-keys";
38 button-powerdn {
45 button-admin {
53 compatible = "gpio-leds";
55 led-0 {
60 led-1 {
65 led-2 {
71 sfp_xg0: dpmac2-sfp {
73 i2c-bus = <&sfplower_i2c>;
74 tx-fault-gpios = <&sfpgpio 0 GPIO_ACTIVE_HIGH>;
75 tx-disable-gpios = <&sfpgpio 1 GPIO_ACTIVE_HIGH>;
76 mod-def0-gpios = <&sfpgpio 2 GPIO_ACTIVE_LOW>;
77 los-gpios = <&sfpgpio 3 GPIO_ACTIVE_HIGH>;
78 maximum-power-milliwatt = <2000>;
81 sfp_xg1: dpmac1-sfp {
83 i2c-bus = <&sfpupper_i2c>;
84 tx-fault-gpios = <&sfpgpio 4 GPIO_ACTIVE_HIGH>;
85 tx-disable-gpios = <&sfpgpio 5 GPIO_ACTIVE_HIGH>;
86 mod-def0-gpios = <&sfpgpio 6 GPIO_ACTIVE_LOW>;
87 los-gpios = <&sfpgpio 7 GPIO_ACTIVE_HIGH>;
88 maximum-power-milliwatt = <2000>;
92 /* XG1 - Upper SFP */
95 pcs-handle = <&pcs1>;
96 phy-connection-type = "10gbase-r";
97 managed = "in-band-status";
100 /* XG0 - Lower SFP */
103 pcs-handle = <&pcs2>;
104 phy-connection-type = "10gbase-r";
105 managed = "in-band-status";
110 phy-handle = <&mdio1_phy5>;
111 phy-connection-type = "qsgmii";
112 managed = "in-band-status";
113 pcs-handle = <&pcs3_0>;
117 phy-handle = <&mdio1_phy6>;
118 phy-connection-type = "qsgmii";
119 managed = "in-band-status";
120 pcs-handle = <&pcs3_1>;
124 phy-handle = <&mdio1_phy7>;
125 phy-connection-type = "qsgmii";
126 managed = "in-band-status";
127 pcs-handle = <&pcs3_2>;
131 phy-handle = <&mdio1_phy8>;
132 phy-connection-type = "qsgmii";
133 managed = "in-band-status";
134 pcs-handle = <&pcs3_3>;
137 /* DPMAC7..10 is GE0 to GE3 */
139 phy-handle = <&mdio1_phy1>;
140 phy-connection-type = "qsgmii";
141 managed = "in-band-status";
142 pcs-handle = <&pcs7_0>;
146 phy-handle = <&mdio1_phy2>;
147 phy-connection-type = "qsgmii";
148 managed = "in-band-status";
149 pcs-handle = <&pcs7_1>;
153 phy-handle = <&mdio1_phy3>;
154 phy-connection-type = "qsgmii";
155 managed = "in-band-status";
156 pcs-handle = <&pcs7_2>;
160 phy-handle = <&mdio1_phy4>;
161 phy-connection-type = "qsgmii";
162 managed = "in-band-status";
163 pcs-handle = <&pcs7_3>;
177 mdio1_phy5: ethernet-phy@c {
181 mdio1_phy6: ethernet-phy@d {
185 mdio1_phy7: ethernet-phy@e {
189 mdio1_phy8: ethernet-phy@f {
193 mdio1_phy1: ethernet-phy@1c {
197 mdio1_phy2: ethernet-phy@1d {
201 mdio1_phy3: ethernet-phy@1e {
205 mdio1_phy4: ethernet-phy@1f {
220 #gpio-cells = <2>;
221 gpio-controller;
223 admin-led-lower-hog {
224 gpio-hog;
226 output-low;
248 i2c-mux@70 {
250 #address-cells = <1>;
251 #size-cells = <0>;
255 #address-cells = <1>;
256 #size-cells = <0>;
261 #address-cells = <1>;
262 #size-cells = <0>;
288 compatible = "jedec,spi-nor";
289 #address-cells = <1>;
290 #size-cells = <1>;
292 spi-max-frequency = <20000000>;
293 spi-rx-bus-width = <4>;
294 spi-tx-bus-width = <4>;
297 compatible = "fixed-partitions";
298 #address-cells = <1>;
299 #size-cells = <1>;
339 compatible = "spi-nand";
340 #address-cells = <1>;
341 #size-cells = <1>;
343 spi-max-frequency = <20000000>;
344 spi-rx-bus-width = <4>;
345 spi-tx-bus-width = <4>;
348 compatible = "fixed-partitions";
349 #address-cells = <1>;
350 #size-cells = <1>;
356 label = "nand-boot-reserved";
366 /* ubia (first OpenWrt) - a/b names to prevent confusion with ubi0/1/etc. */