Lines Matching +full:0 +full:x00030001
38 #size-cells = <0>;
40 cpu0: cpu@0 {
43 reg = <0x0>;
44 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
53 reg = <0x1>;
54 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
63 reg = <0x2>;
64 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
73 reg = <0x3>;
74 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
97 arm,psci-suspend-param = <0x0>;
107 reg = <0x0 0x80000000 0x0 0x0>;
112 #clock-cells = <0>;
120 offset = <0xb0>;
121 mask = <0x02>;
128 thermal-sensors = <&tmu 0>;
239 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) |
241 <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) |
243 <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) |
245 <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) |
265 reg = <0x0 0x1410000 0 0x10000>, /* GICD */
266 <0x0 0x1420000 0 0x20000>, /* GICC */
267 <0x0 0x1440000 0 0x20000>, /* GICH */
268 <0x0 0x1460000 0 0x20000>; /* GICV */
269 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) |
278 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
283 reg = <0x0 0x1080000 0x0 0x1000>;
289 reg = <0x0 0x1530000 0x0 0x10000>;
297 #size-cells = <0>;
298 reg = <0x0 0x1550000 0x0 0x10000>,
299 <0x0 0x40000000 0x0 0x10000000>;
312 reg = <0x0 0x1560000 0x0 0x10000>;
322 reg = <0x0 0x1570000 0x0 0x10000>;
326 ranges = <0x0 0x0 0x1570000 0x10000>;
331 #address-cells = <0>;
333 reg = <0x1ac 4>;
335 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
336 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
337 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
338 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
339 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
340 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
341 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
342 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
343 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
344 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
345 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
346 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
347 interrupt-map-mask = <0xf 0x0>;
352 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
353 "fsl,sec-v4.0";
357 ranges = <0x0 0x00 0x1700000 0x100000>;
358 reg = <0x00 0x1700000 0x0 0x100000>;
363 "fsl,sec-v5.0-job-ring",
364 "fsl,sec-v4.0-job-ring";
365 reg = <0x10000 0x10000>;
371 "fsl,sec-v5.0-job-ring",
372 "fsl,sec-v4.0-job-ring";
373 reg = <0x20000 0x10000>;
379 "fsl,sec-v5.0-job-ring",
380 "fsl,sec-v4.0-job-ring";
381 reg = <0x30000 0x10000>;
387 "fsl,sec-v5.0-job-ring",
388 "fsl,sec-v4.0-job-ring";
389 reg = <0x40000 0x10000>;
396 reg = <0x0 0x1880000 0x0 0x10000>;
404 reg = <0x0 0x1890000 0x0 0x10000>;
411 ranges = <0x0 0x5 0x00000000 0x8000000>;
415 ranges = <0x0 0x5 0x08000000 0x8000000>;
420 reg = <0x0 0x1e80000 0x0 0x10000>;
428 reg = <0x0 0x1ee0000 0x0 0x1000>;
434 reg = <0x0 0x1ee1000 0x0 0x1000>;
441 reg = <0x0 0x1f00000 0x0 0x10000>;
443 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
446 <0x00000000 0x00000023>,
447 <0x00000001 0x00000029>,
448 <0x00000002 0x0000002f>,
449 <0x00000003 0x00000036>,
450 <0x00000004 0x0000003c>,
451 <0x00000005 0x00000042>,
452 <0x00000006 0x00000049>,
453 <0x00000007 0x0000004f>,
454 <0x00000008 0x00000055>,
455 <0x00000009 0x0000005c>,
456 <0x0000000a 0x00000062>,
457 <0x0000000b 0x00000068>,
459 <0x00010000 0x00000022>,
460 <0x00010001 0x0000002a>,
461 <0x00010002 0x00000032>,
462 <0x00010003 0x0000003a>,
463 <0x00010004 0x00000042>,
464 <0x00010005 0x0000004a>,
465 <0x00010006 0x00000052>,
466 <0x00010007 0x0000005a>,
467 <0x00010008 0x00000062>,
468 <0x00010009 0x0000006a>,
470 <0x00020000 0x00000021>,
471 <0x00020001 0x0000002b>,
472 <0x00020002 0x00000035>,
473 <0x00020003 0x0000003e>,
474 <0x00020004 0x00000048>,
475 <0x00020005 0x00000052>,
476 <0x00020006 0x0000005c>,
478 <0x00030000 0x00000011>,
479 <0x00030001 0x0000001a>,
480 <0x00030002 0x00000024>,
481 <0x00030003 0x0000002e>,
482 <0x00030004 0x00000038>,
483 <0x00030005 0x00000042>,
484 <0x00030006 0x0000004c>,
485 <0x00030007 0x00000056>;
490 compatible = "fsl,ls1021a-v1.0-dspi";
492 #size-cells = <0>;
493 reg = <0x0 0x2100000 0x0 0x10000>;
506 #size-cells = <0>;
507 reg = <0x0 0x2180000 0x0 0x10000>;
520 #size-cells = <0>;
521 reg = <0x0 0x2190000 0x0 0x10000>;
532 #size-cells = <0>;
533 reg = <0x0 0x21a0000 0x0 0x10000>;
544 #size-cells = <0>;
545 reg = <0x0 0x21b0000 0x0 0x10000>;
555 reg = <0x00 0x21c0500 0x0 0x100>;
564 reg = <0x00 0x21c0600 0x0 0x100>;
573 reg = <0x0 0x21d0500 0x0 0x100>;
582 reg = <0x0 0x21d0600 0x0 0x100>;
591 reg = <0x0 0x2300000 0x0 0x10000>;
601 reg = <0x0 0x2310000 0x0 0x10000>;
611 reg = <0x0 0x2320000 0x0 0x10000>;
621 reg = <0x0 0x2330000 0x0 0x10000>;
631 reg = <0x0 0x2950000 0x0 0x1000>;
641 reg = <0x0 0x2960000 0x0 0x1000>;
651 reg = <0x0 0x2970000 0x0 0x1000>;
661 reg = <0x0 0x2980000 0x0 0x1000>;
671 reg = <0x0 0x2990000 0x0 0x1000>;
681 reg = <0x0 0x29a0000 0x0 0x1000>;
691 reg = <0x0 0x2ad0000 0x0 0x10000>;
700 reg = <0x0 0x2c00000 0x0 0x10000>,
701 <0x0 0x2c10000 0x0 0x10000>,
702 <0x0 0x2c20000 0x0 0x10000>;
720 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
724 reg = <0x0 0x2f00000 0x0 0x10000>;
727 snps,quirk-frame-length-adjustment = <0x20>;
735 reg = <0x0 0x3000000 0x0 0x10000>;
738 snps,quirk-frame-length-adjustment = <0x20>;
746 reg = <0x0 0x3100000 0x0 0x10000>;
749 snps,quirk-frame-length-adjustment = <0x20>;
757 reg = <0x0 0x3200000 0x0 0x10000>,
758 <0x0 0x20140520 0x0 0x4>;
769 reg = <0x0 0x1580000 0x0 0x10000>;
779 reg = <0x0 0x1590000 0x0 0x10000>;
789 reg = <0x0 0x15a0000 0x0 0x10000>;
798 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
799 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
808 bus-range = <0x0 0xff>;
809 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
810 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
813 interrupt-map-mask = <0 0 0 7>;
814 interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
815 <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
816 <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
817 <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
824 reg = <0x00 0x03400000 0x0 0x00100000>,
825 <0x40 0x00000000 0x8 0x00000000>;
837 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
838 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
847 bus-range = <0x0 0xff>;
848 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
849 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
852 interrupt-map-mask = <0 0 0 7>;
853 interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
854 <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
855 <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
856 <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
863 reg = <0x00 0x03500000 0x0 0x00100000>,
864 <0x48 0x00000000 0x8 0x00000000>;
876 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
877 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
886 bus-range = <0x0 0xff>;
887 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
888 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
891 interrupt-map-mask = <0 0 0 7>;
892 interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
893 <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
894 <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
895 <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
902 reg = <0x00 0x03600000 0x0 0x00100000>,
903 <0x50 0x00000000 0x8 0x00000000>;
915 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
916 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
917 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
928 block-offset = <0x10000>;
937 reg = <0x0 0x1ee2140 0x0 0x4>;
943 reg = <0x0 0x29d0000 0x0 0x10000>;
944 fsl,rcpm-wakeup = <&rcpm 0x20000>;
957 size = <0 0x1000000>;
958 alignment = <0 0x1000000>;
964 size = <0 0x800000>;
965 alignment = <0 0x800000>;
971 size = <0 0x2000000>;
972 alignment = <0 0x2000000>;