Lines Matching +full:10 +full:gbase +full:- +full:r

1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3  * Device Tree Include file for Freescale Layerscape-1046A family SoC.
6  * Copyright 2019-2020 NXP
11 /dts-v1/;
13 #include "fsl-ls1046a.dtsi"
17 	compatible = "fsl,ls1046a-rdb", "fsl,ls1046a";
27 		stdout-path = "serial0:115200n8";
40 	mmc-hs200-1_8v;
41 	sd-uhs-sdr104;
42 	sd-uhs-sdr50;
43 	sd-uhs-sdr25;
44 	sd-uhs-sdr12;
53 		shunt-resistor = <1000>;
56 	temp-sensor@4c {
73 		/* IRQ_RTC_B -> IRQ05, active low */
74 		interrupts-extended = <&extirq 5 IRQ_TYPE_LEVEL_LOW>;
79 	#address-cells = <2>;
80 	#size-cells = <1>;
87 		compatible = "fsl,ifc-nand";
88 		#address-cells = <1>;
89 		#size-cells = <1>;
93 	cpld: board-control@2,0 {
94 		compatible = "fsl,ls1046ardb-cpld";
103 		compatible = "jedec,spi-nor";
104 		#address-cells = <1>;
105 		#size-cells = <1>;
106 		spi-max-frequency = <50000000>;
107 		spi-rx-bus-width = <4>;
108 		spi-tx-bus-width = <1>;
113 		compatible = "jedec,spi-nor";
114 		#address-cells = <1>;
115 		#size-cells = <1>;
116 		spi-max-frequency = <50000000>;
117 		spi-rx-bus-width = <4>;
118 		spi-tx-bus-width = <1>;
127 #include "fsl-ls1046-post.dtsi"
131 		phy-handle = <&rgmii_phy1>;
132 		phy-connection-type = "rgmii-id";
136 		phy-handle = <&rgmii_phy2>;
137 		phy-connection-type = "rgmii-id";
141 		phy-handle = <&sgmii_phy1>;
142 		phy-connection-type = "sgmii";
146 		phy-handle = <&sgmii_phy2>;
147 		phy-connection-type = "sgmii";
150 	ethernet@f0000 { /* 10GEC1 */
151 		phy-handle = <&aqr106_phy>;
152 		phy-connection-type = "xgmii";
155 	ethernet@f2000 { /* 10GEC2 */
156 		phy-connection-type = "10gbase-r";
157 		managed = "in-band-status";
161 		rgmii_phy1: ethernet-phy@1 {
165 		rgmii_phy2: ethernet-phy@2 {
169 		sgmii_phy1: ethernet-phy@3 {
173 		sgmii_phy2: ethernet-phy@4 {
179 		aqr106_phy: ethernet-phy@0 {
180 			compatible = "ethernet-phy-ieee802.3-c45";