Lines Matching +full:0 +full:x2100000
37 #size-cells = <0>;
45 cpu0: cpu@0 {
48 reg = <0x0>;
49 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
58 reg = <0x1>;
59 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
68 reg = <0x2>;
69 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
78 reg = <0x3>;
79 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
102 arm,psci-suspend-param = <0x0>;
111 reg = <0x0 0x80000000 0 0x80000000>;
122 size = <0 0x1000000>;
123 alignment = <0 0x1000000>;
129 size = <0 0x400000>;
130 alignment = <0 0x400000>;
136 size = <0 0x2000000>;
137 alignment = <0 0x2000000>;
144 #clock-cells = <0>;
152 offset = <0xb0>;
153 mask = <0x02>;
160 thermal-sensors = <&tmu 0>;
294 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
295 <0x0 0x1402000 0 0x2000>, /* GICC */
296 <0x0 0x1404000 0 0x2000>, /* GICH */
297 <0x0 0x1406000 0 0x2000>; /* GICV */
306 dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
311 reg = <0x0 0x1ee1000 0x0 0x1000>;
318 reg = <0x0 0x1570000 0x0 0x10000>;
322 ranges = <0x0 0x0 0x1570000 0x10000>;
327 #address-cells = <0>;
329 reg = <0x1ac 4>;
331 <0 0 &gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
332 <1 0 &gic GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
333 <2 0 &gic GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
334 <3 0 &gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
335 <4 0 &gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
336 <5 0 &gic GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
337 <6 0 &gic GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
338 <7 0 &gic GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
339 <8 0 &gic GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
340 <9 0 &gic GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
341 <10 0 &gic GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
342 <11 0 &gic GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
343 interrupt-map-mask = <0xf 0x0>;
348 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
349 "fsl,sec-v4.0";
353 ranges = <0x0 0x00 0x1700000 0x100000>;
354 reg = <0x00 0x1700000 0x0 0x100000>;
360 "fsl,sec-v5.0-job-ring",
361 "fsl,sec-v4.0-job-ring";
362 reg = <0x10000 0x10000>;
368 "fsl,sec-v5.0-job-ring",
369 "fsl,sec-v4.0-job-ring";
370 reg = <0x20000 0x10000>;
376 "fsl,sec-v5.0-job-ring",
377 "fsl,sec-v4.0-job-ring";
378 reg = <0x30000 0x10000>;
384 "fsl,sec-v5.0-job-ring",
385 "fsl,sec-v4.0-job-ring";
386 reg = <0x40000 0x10000>;
393 reg = <0x0 0x1e80000 0x0 0x10000>;
401 reg = <0x0 0x1ee0000 0x0 0x1000>;
407 reg = <0x0 0x1530000 0x0 0x10000>;
414 #size-cells = <0>;
415 reg = <0x0 0x1550000 0x0 0x10000>,
416 <0x0 0x40000000 0x0 0x4000000>;
429 reg = <0x0 0x1560000 0x0 0x10000>;
431 clock-frequency = <0>;
439 reg = <0x0 0x1080000 0x0 0x1000>;
445 reg = <0x0 0x1f00000 0x0 0x10000>;
447 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>;
449 <0x00000000 0x00000023>,
450 <0x00000001 0x0000002a>,
451 <0x00000002 0x00000031>,
452 <0x00000003 0x00000037>,
453 <0x00000004 0x0000003e>,
454 <0x00000005 0x00000044>,
455 <0x00000006 0x0000004b>,
456 <0x00000007 0x00000051>,
457 <0x00000008 0x00000058>,
458 <0x00000009 0x0000005e>,
459 <0x0000000a 0x00000065>,
460 <0x0000000b 0x0000006b>,
462 <0x00010000 0x00000023>,
463 <0x00010001 0x0000002b>,
464 <0x00010002 0x00000033>,
465 <0x00010003 0x0000003b>,
466 <0x00010004 0x00000043>,
467 <0x00010005 0x0000004b>,
468 <0x00010006 0x00000054>,
469 <0x00010007 0x0000005c>,
470 <0x00010008 0x00000064>,
471 <0x00010009 0x0000006c>,
473 <0x00020000 0x00000021>,
474 <0x00020001 0x0000002c>,
475 <0x00020002 0x00000036>,
476 <0x00020003 0x00000040>,
477 <0x00020004 0x0000004b>,
478 <0x00020005 0x00000055>,
479 <0x00020006 0x0000005f>,
481 <0x00030000 0x00000013>,
482 <0x00030001 0x0000001d>,
483 <0x00030002 0x00000028>,
484 <0x00030003 0x00000032>,
485 <0x00030004 0x0000003d>,
486 <0x00030005 0x00000047>,
487 <0x00030006 0x00000052>,
488 <0x00030007 0x0000005c>;
494 reg = <0x0 0x1880000 0x0 0x10000>;
501 reg = <0x0 0x1890000 0x0 0x10000>;
507 ranges = <0x0 0x5 0x08000000 0x8000000>;
511 ranges = <0x0 0x5 0x00000000 0x8000000>;
515 compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi";
517 #size-cells = <0>;
518 reg = <0x0 0x2100000 0x0 0x10000>;
531 #size-cells = <0>;
532 reg = <0x0 0x2180000 0x0 0x10000>;
546 #size-cells = <0>;
547 reg = <0x0 0x2190000 0x0 0x10000>;
562 #size-cells = <0>;
563 reg = <0x0 0x21a0000 0x0 0x10000>;
578 #size-cells = <0>;
579 reg = <0x0 0x21b0000 0x0 0x10000>;
593 reg = <0x00 0x21c0500 0x0 0x100>;
601 reg = <0x00 0x21c0600 0x0 0x100>;
609 reg = <0x0 0x21d0500 0x0 0x100>;
617 reg = <0x0 0x21d0600 0x0 0x100>;
625 reg = <0x0 0x2300000 0x0 0x10000>;
635 reg = <0x0 0x2310000 0x0 0x10000>;
645 reg = <0x0 0x2320000 0x0 0x10000>;
655 reg = <0x0 0x2330000 0x0 0x10000>;
667 ranges = <0x0 0x0 0x2400000 0x40000>;
668 reg = <0x0 0x2400000 0x0 0x480>;
676 reg = <0x80 0x80>;
686 reg = <0x700 0x80>;
692 reg = <0x1000 0x800>;
697 reg = <0x2000 0x200>;
704 reg = <0x2200 0x200>;
713 ranges = <0x0 0x10000 0x6000>;
715 data-only@0 {
718 reg = <0x0 0x6000>;
725 reg = <0x0 0x2950000 0x0 0x1000>;
727 clocks = <&clockgen QORIQ_CLK_SYSCLK 0>;
737 reg = <0x0 0x2960000 0x0 0x1000>;
750 reg = <0x0 0x2970000 0x0 0x1000>;
763 reg = <0x0 0x2980000 0x0 0x1000>;
776 reg = <0x0 0x2990000 0x0 0x1000>;
789 reg = <0x0 0x29a0000 0x0 0x1000>;
802 reg = <0x0 0x2ad0000 0x0 0x10000>;
812 reg = <0x0 0x2c00000 0x0 0x10000>,
813 <0x0 0x2c10000 0x0 0x10000>,
814 <0x0 0x2c20000 0x0 0x10000>;
832 dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>;
836 reg = <0x0 0x2f00000 0x0 0x10000>;
839 snps,quirk-frame-length-adjustment = <0x20>;
848 reg = <0x0 0x3000000 0x0 0x10000>;
851 snps,quirk-frame-length-adjustment = <0x20>;
860 reg = <0x0 0x3100000 0x0 0x10000>;
863 snps,quirk-frame-length-adjustment = <0x20>;
872 reg = <0x0 0x3200000 0x0 0x10000>,
873 <0x0 0x20140520 0x0 0x4>;
884 reg = <0x0 0x1571000 0x0 0x8>;
891 reg = <0x0 0x1572000 0x0 0x8>;
898 reg = <0x0 0x1573000 0x0 0x8>;
905 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
906 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
915 bus-range = <0x0 0xff>;
916 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
917 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
920 interrupt-map-mask = <0 0 0 7>;
921 interrupt-map = <0000 0 0 1 &gic 0 110 0x4>,
922 <0000 0 0 2 &gic 0 111 0x4>,
923 <0000 0 0 3 &gic 0 112 0x4>,
924 <0000 0 0 4 &gic 0 113 0x4>;
925 fsl,pcie-scfg = <&scfg 0>;
932 reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
933 <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
942 bus-range = <0x0 0xff>;
943 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
944 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
947 interrupt-map-mask = <0 0 0 7>;
948 interrupt-map = <0000 0 0 1 &gic 0 120 0x4>,
949 <0000 0 0 2 &gic 0 121 0x4>,
950 <0000 0 0 3 &gic 0 122 0x4>,
951 <0000 0 0 4 &gic 0 123 0x4>;
959 reg = <0x00 0x03600000 0x0 0x00100000>, /* controller registers */
960 <0x50 0x00000000 0x0 0x00002000>; /* configuration space */
969 bus-range = <0x0 0xff>;
970 ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */
971 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
974 interrupt-map-mask = <0 0 0 7>;
975 interrupt-map = <0000 0 0 1 &gic 0 154 0x4>,
976 <0000 0 0 2 &gic 0 155 0x4>,
977 <0000 0 0 3 &gic 0 156 0x4>,
978 <0000 0 0 4 &gic 0 157 0x4>;
986 reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
987 <0x0 0x8390000 0x0 0x10000>, /* Status regs */
988 <0x0 0x83a0000 0x0 0x40000>; /* Block regs */
999 block-offset = <0x10000>;
1008 reg = <0x0 0x1ee2140 0x0 0x4>;
1014 reg = <0x0 0x29d0000 0x0 0x10000>;
1015 fsl,rcpm-wakeup = <&rcpm 0x20000>;