Lines Matching +full:mdio +full:- +full:mux +full:- +full:multiplexer
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
32 stdout-path = "serial0:115200n8";
40 sys_mclk: clock-mclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
46 reg_1p8v: regulator-1p8v {
47 compatible = "regulator-fixed";
48 regulator-name = "1P8V";
49 regulator-min-microvolt = <1800000>;
50 regulator-max-microvolt = <1800000>;
51 regulator-always-on;
54 sb_3v3: regulator-sb3v3 {
55 compatible = "regulator-fixed";
56 regulator-name = "3v3_vbus";
57 regulator-min-microvolt = <3300000>;
58 regulator-max-microvolt = <3300000>;
59 regulator-boot-on;
60 regulator-always-on;
64 compatible = "simple-audio-card";
65 simple-audio-card,format = "i2s";
66 simple-audio-card,widgets =
71 simple-audio-card,routing =
78 simple-audio-card,cpu {
79 sound-dai = <&sai1>;
80 frame-master;
81 bitclock-master;
84 simple-audio-card,codec {
85 sound-dai = <&sgtl5000>;
86 frame-master;
87 bitclock-master;
88 system-clock-frequency = <25000000>;
92 mdio-mux {
93 compatible = "mdio-mux-multiplexer";
94 mux-controls = <&mux 0>;
95 mdio-parent-bus = <&enetc_mdio_pf3>;
96 #address-cells = <1>;
97 #size-cells = <0>;
99 /* on-board RGMII PHY */
100 mdio@0 {
101 #address-cells = <1>;
102 #size-cells = <0>;
105 qds_phy1: ethernet-phy@5 {
111 mdio_slot1: mdio@4 {
112 #address-cells = <1>;
113 #size-cells = <0>;
117 mdio_slot2: mdio@5 {
118 #address-cells = <1>;
119 #size-cells = <0>;
123 mdio_slot3: mdio@6 {
124 #address-cells = <1>;
125 #size-cells = <0>;
129 mdio_slot4: mdio@7 {
130 #address-cells = <1>;
131 #size-cells = <0>;
146 bus-num = <0>;
150 #address-cells = <1>;
151 #size-cells = <1>;
152 compatible = "jedec,spi-nor";
153 spi-cpol;
154 spi-cpha;
156 spi-max-frequency = <10000000>;
160 #address-cells = <1>;
161 #size-cells = <1>;
162 compatible = "jedec,spi-nor";
163 spi-cpol;
164 spi-cpha;
166 spi-max-frequency = <10000000>;
170 #address-cells = <1>;
171 #size-cells = <1>;
172 compatible = "jedec,spi-nor";
173 spi-cpol;
174 spi-cpha;
176 spi-max-frequency = <10000000>;
181 bus-num = <1>;
185 #address-cells = <1>;
186 #size-cells = <1>;
187 compatible = "jedec,spi-nor";
188 spi-cpol;
189 spi-cpha;
191 spi-max-frequency = <10000000>;
195 #address-cells = <1>;
196 #size-cells = <1>;
197 compatible = "jedec,spi-nor";
198 spi-cpol;
199 spi-cpha;
201 spi-max-frequency = <10000000>;
205 #address-cells = <1>;
206 #size-cells = <1>;
207 compatible = "jedec,spi-nor";
208 spi-cpol;
209 spi-cpha;
211 spi-max-frequency = <10000000>;
216 bus-num = <2>;
220 #address-cells = <1>;
221 #size-cells = <1>;
222 compatible = "jedec,spi-nor";
223 spi-cpol;
224 spi-cpha;
226 spi-max-frequency = <10000000>;
239 phy-handle = <&qds_phy1>;
240 phy-mode = "rgmii-id";
260 compatible = "jedec,spi-nor";
261 #address-cells = <1>;
262 #size-cells = <1>;
263 spi-max-frequency = <50000000>;
264 /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */
265 spi-rx-bus-width = <8>; /* 8 SPI Rx lines */
266 spi-tx-bus-width = <1>; /* 1 SPI Tx line */
278 i2c-mux@77 {
281 #address-cells = <1>;
282 #size-cells = <0>;
285 #address-cells = <1>;
286 #size-cells = <0>;
289 current-monitor@40 {
292 shunt-resistor = <1000>;
295 current-monitor@41 {
298 shunt-resistor = <1000>;
303 #address-cells = <1>;
304 #size-cells = <0>;
307 temperature-sensor@4c {
310 vcc-supply = <&sb_3v3>;
325 #address-cells = <1>;
326 #size-cells = <0>;
329 sgtl5000: audio-codec@a {
330 #sound-dai-cells = <0>;
333 VDDA-supply = <®_1p8v>;
334 VDDIO-supply = <®_1p8v>;
341 compatible = "fsl,ls1028aqds-fpga", "fsl,fpga-qixis-i2c",
342 "simple-mfd";
345 mux: mux-controller { label
346 compatible = "reg-mux";
347 #mux-control-cells = <1>;
348 mux-reg-masks = <0x54 0xf0>; /* 0: reg 0x54, bits 7:4 */