Lines Matching +full:0 +full:x00020006
32 #size-cells = <0>;
34 cpu0: cpu@0 {
37 reg = <0x0>;
38 clocks = <&clockgen QORIQ_CLK_CMUX 0>;
54 arm,psci-suspend-param = <0x0>;
63 #clock-cells = <0>;
70 #clock-cells = <0>;
92 reg = <0x0 0x1401000 0 0x1000>, /* GICD */
93 <0x0 0x1402000 0 0x2000>, /* GICC */
94 <0x0 0x1404000 0 0x2000>, /* GICH */
95 <0x0 0x1406000 0 0x2000>; /* GICV */
102 offset = <0xb0>;
103 mask = <0x02>;
110 thermal-sensors = <&tmu 0>;
146 #size-cells = <0>;
147 reg = <0x0 0x1550000 0x0 0x10000>,
148 <0x0 0x40000000 0x0 0x10000000>;
161 reg = <0x0 0x1560000 0x0 0x10000>;
173 reg = <0x0 0x1570000 0x0 0x10000>;
179 reg = <0x0 0x1580000 0x0 0x10000>;
191 compatible = "fsl,sec-v5.4", "fsl,sec-v5.0",
192 "fsl,sec-v4.0";
196 ranges = <0x0 0x00 0x1700000 0x100000>;
197 reg = <0x00 0x1700000 0x0 0x100000>;
203 "fsl,sec-v5.0-job-ring",
204 "fsl,sec-v4.0-job-ring";
205 reg = <0x10000 0x10000>;
211 "fsl,sec-v5.0-job-ring",
212 "fsl,sec-v4.0-job-ring";
213 reg = <0x20000 0x10000>;
219 "fsl,sec-v5.0-job-ring",
220 "fsl,sec-v4.0-job-ring";
221 reg = <0x30000 0x10000>;
227 "fsl,sec-v5.0-job-ring",
228 "fsl,sec-v4.0-job-ring";
229 reg = <0x40000 0x10000>;
235 "fsl,sec-v5.0-rtic",
236 "fsl,sec-v4.0-rtic";
239 reg = <0x60000 0x100>, <0x60e00 0x18>;
240 ranges = <0x0 0x60100 0x500>;
242 rtic_a: rtic-a@0 {
244 "fsl,sec-v5.0-rtic-memory",
245 "fsl,sec-v4.0-rtic-memory";
246 reg = <0x00 0x20>, <0x100 0x100>;
251 "fsl,sec-v5.0-rtic-memory",
252 "fsl,sec-v4.0-rtic-memory";
253 reg = <0x20 0x20>, <0x200 0x100>;
258 "fsl,sec-v5.0-rtic-memory",
259 "fsl,sec-v4.0-rtic-memory";
260 reg = <0x40 0x20>, <0x300 0x100>;
265 "fsl,sec-v5.0-rtic-memory",
266 "fsl,sec-v4.0-rtic-memory";
267 reg = <0x60 0x20>, <0x400 0x100>;
274 reg = <0x0 0x1e80000 0x0 0x10000>;
281 compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
282 "fsl,sec-v4.0-mon";
283 reg = <0x0 0x1e90000 0x0 0x10000>;
291 reg = <0x0 0x1ee0000 0x0 0x1000>;
297 reg = <0x0 0x1ee1000 0x0 0x1000>;
305 reg = <0x0 0x1f00000 0x0 0x10000>;
307 fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>;
309 <0x00000000 0x00000025>,
310 <0x00000001 0x0000002c>,
311 <0x00000002 0x00000032>,
312 <0x00000003 0x00000039>,
313 <0x00000004 0x0000003f>,
314 <0x00000005 0x00000046>,
315 <0x00000006 0x0000004c>,
316 <0x00000007 0x00000053>,
317 <0x00000008 0x00000059>,
318 <0x00000009 0x0000005f>,
319 <0x0000000a 0x00000066>,
320 <0x0000000b 0x0000006c>,
322 <0x00010000 0x00000026>,
323 <0x00010001 0x0000002d>,
324 <0x00010002 0x00000035>,
325 <0x00010003 0x0000003d>,
326 <0x00010004 0x00000045>,
327 <0x00010005 0x0000004d>,
328 <0x00010006 0x00000055>,
329 <0x00010007 0x0000005d>,
330 <0x00010008 0x00000065>,
331 <0x00010009 0x0000006d>,
333 <0x00020000 0x00000026>,
334 <0x00020001 0x00000030>,
335 <0x00020002 0x0000003a>,
336 <0x00020003 0x00000044>,
337 <0x00020004 0x0000004e>,
338 <0x00020005 0x00000059>,
339 <0x00020006 0x00000063>,
341 <0x00030000 0x00000014>,
342 <0x00030001 0x00000021>,
343 <0x00030002 0x0000002e>,
344 <0x00030003 0x0000003a>,
345 <0x00030004 0x00000047>,
346 <0x00030005 0x00000053>,
347 <0x00030006 0x00000060>;
354 #size-cells = <0>;
355 reg = <0x0 0x2180000 0x0 0x10000>;
359 scl-gpios = <&gpio0 2 0>;
366 #size-cells = <0>;
367 reg = <0x0 0x2190000 0x0 0x10000>;
371 scl-gpios = <&gpio0 13 0>;
376 compatible = "fsl,ls1012a-dspi", "fsl,ls1021a-v1.0-dspi";
378 #size-cells = <0>;
379 reg = <0x0 0x2100000 0x0 0x10000>;
391 reg = <0x00 0x21c0500 0x0 0x100>;
400 reg = <0x00 0x21c0600 0x0 0x100>;
409 reg = <0x0 0x2300000 0x0 0x10000>;
419 reg = <0x0 0x2310000 0x0 0x10000>;
430 reg = <0x0 0x2ad0000 0x0 0x10000>;
437 #sound-dai-cells = <0>;
439 reg = <0x0 0x2b50000 0x0 0x10000>;
457 #sound-dai-cells = <0>;
459 reg = <0x0 0x2b60000 0x0 0x10000>;
479 reg = <0x0 0x2c00000 0x0 0x10000>,
480 <0x0 0x2c10000 0x0 0x10000>,
481 <0x0 0x2c20000 0x0 0x10000>;
496 reg = <0x0 0x2f00000 0x0 0x10000>;
499 snps,quirk-frame-length-adjustment = <0x20>;
506 reg = <0x0 0x3200000 0x0 0x10000>,
507 <0x0 0x20140520 0x0 0x4>;
518 reg = <0x0 0x8600000 0x0 0x1000>;
526 reg = <0x0 0x1572000 0x0 0x8>;
533 reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */
534 <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
542 bus-range = <0x0 0xff>;
543 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
544 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
547 interrupt-map-mask = <0 0 0 7>;
548 interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>,
549 <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>,
550 <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>,
551 <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
558 reg = <0x0 0x1ee2140 0x0 0x4>;
564 reg = <0x0 0x29d0000 0x0 0x10000>;
565 fsl,rcpm-wakeup = <&rcpm 0x20000>;