Lines Matching +full:d +full:- +full:cache +full:- +full:sets
1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/samsung,exynosautov920.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/soc/samsung,exynos-usi.h>
15 #address-cells = <2>;
16 #size-cells = <1>;
18 interrupt-parent = <&gic>;
31 arm-pmu {
32 compatible = "arm,cortex-a78-pmu";
37 compatible = "fixed-clock";
38 #clock-cells = <0>;
39 clock-output-names = "oscclk";
43 #address-cells = <2>;
44 #size-cells = <0>;
46 cpu-map {
89 compatible = "arm,cortex-a78ae";
91 enable-method = "psci";
92 i-cache-size = <0x10000>;
93 i-cache-line-size = <64>;
94 i-cache-sets = <256>;
95 d-cache-size = <0x10000>;
96 d-cache-line-size = <64>;
97 d-cache-sets = <256>;
98 next-level-cache = <&l2_cache_cl0>;
103 compatible = "arm,cortex-a78ae";
105 enable-method = "psci";
106 i-cache-size = <0x10000>;
107 i-cache-line-size = <64>;
108 i-cache-sets = <256>;
109 d-cache-size = <0x10000>;
110 d-cache-line-size = <64>;
111 d-cache-sets = <256>;
112 next-level-cache = <&l2_cache_cl0>;
117 compatible = "arm,cortex-a78ae";
119 enable-method = "psci";
120 i-cache-size = <0x10000>;
121 i-cache-line-size = <64>;
122 i-cache-sets = <256>;
123 d-cache-size = <0x10000>;
124 d-cache-line-size = <64>;
125 d-cache-sets = <256>;
126 next-level-cache = <&l2_cache_cl0>;
131 compatible = "arm,cortex-a78ae";
133 enable-method = "psci";
134 i-cache-size = <0x10000>;
135 i-cache-line-size = <64>;
136 i-cache-sets = <256>;
137 d-cache-size = <0x10000>;
138 d-cache-line-size = <64>;
139 d-cache-sets = <256>;
140 next-level-cache = <&l2_cache_cl0>;
145 compatible = "arm,cortex-a78ae";
147 enable-method = "psci";
148 i-cache-size = <0x10000>;
149 i-cache-line-size = <64>;
150 i-cache-sets = <256>;
151 d-cache-size = <0x10000>;
152 d-cache-line-size = <64>;
153 d-cache-sets = <256>;
154 next-level-cache = <&l2_cache_cl1>;
159 compatible = "arm,cortex-a78ae";
161 enable-method = "psci";
162 i-cache-size = <0x10000>;
163 i-cache-line-size = <64>;
164 i-cache-sets = <256>;
165 d-cache-size = <0x10000>;
166 d-cache-line-size = <64>;
167 d-cache-sets = <256>;
168 next-level-cache = <&l2_cache_cl1>;
173 compatible = "arm,cortex-a78ae";
175 enable-method = "psci";
176 i-cache-size = <0x10000>;
177 i-cache-line-size = <64>;
178 i-cache-sets = <256>;
179 d-cache-size = <0x10000>;
180 d-cache-line-size = <64>;
181 d-cache-sets = <256>;
182 next-level-cache = <&l2_cache_cl1>;
187 compatible = "arm,cortex-a78ae";
189 enable-method = "psci";
190 i-cache-size = <0x10000>;
191 i-cache-line-size = <64>;
192 i-cache-sets = <256>;
193 d-cache-size = <0x10000>;
194 d-cache-line-size = <64>;
195 d-cache-sets = <256>;
196 next-level-cache = <&l2_cache_cl1>;
201 compatible = "arm,cortex-a78ae";
203 enable-method = "psci";
204 i-cache-size = <0x10000>;
205 i-cache-line-size = <64>;
206 i-cache-sets = <256>;
207 d-cache-size = <0x10000>;
208 d-cache-line-size = <64>;
209 d-cache-sets = <256>;
210 next-level-cache = <&l2_cache_cl2>;
215 compatible = "arm,cortex-a78ae";
217 enable-method = "psci";
218 i-cache-size = <0x10000>;
219 i-cache-line-size = <64>;
220 i-cache-sets = <256>;
221 d-cache-size = <0x10000>;
222 d-cache-line-size = <64>;
223 d-cache-sets = <256>;
224 next-level-cache = <&l2_cache_cl2>;
227 l2_cache_cl0: l2-cache0 {
228 compatible = "cache";
229 cache-level = <2>;
230 cache-unified;
231 cache-size = <0x40000>;
232 cache-line-size = <64>;
233 cache-sets = <512>;
234 next-level-cache = <&l3_cache_cl0>;
237 l2_cache_cl1: l2-cache1 {
238 compatible = "cache";
239 cache-level = <2>;
240 cache-unified;
241 cache-size = <0x40000>;
242 cache-line-size = <64>;
243 cache-sets = <512>;
244 next-level-cache = <&l3_cache_cl1>;
247 l2_cache_cl2: l2-cache2 {
248 compatible = "cache";
249 cache-level = <2>;
250 cache-unified;
251 cache-size = <0x40000>;
252 cache-line-size = <64>;
253 cache-sets = <512>;
254 next-level-cache = <&l3_cache_cl2>;
257 l3_cache_cl0: l3-cache0 {
258 compatible = "cache";
259 cache-level = <3>;
260 cache-unified;
261 cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-0 */
262 cache-line-size = <64>;
263 cache-sets = <2048>;
266 l3_cache_cl1: l3-cache1 {
267 compatible = "cache";
268 cache-level = <3>;
269 cache-unified;
270 cache-size = <0x200000>;/* 2MB L3 cache for cpu cluster-1 */
271 cache-line-size = <64>;
272 cache-sets = <2048>;
275 l3_cache_cl2: l3-cache2 {
276 compatible = "cache";
277 cache-level = <3>;
278 cache-unified;
279 cache-size = <0x100000>;/* 1MB L3 cache for cpu cluster-2 */
280 cache-line-size = <64>;
281 cache-sets = <1365>;
286 compatible = "arm,psci-1.0";
291 compatible = "simple-bus";
292 #address-cells = <1>;
293 #size-cells = <1>;
297 compatible = "samsung,exynosautov920-chipid",
298 "samsung,exynos850-chipid";
302 cmu_misc: clock-controller@10020000 {
303 compatible = "samsung,exynosautov920-cmu-misc";
305 #clock-cells = <1>;
309 clock-names = "oscclk",
314 compatible = "samsung,exynosautov920-wdt";
318 clock-names = "watchdog", "watchdog_src";
319 samsung,syscon-phandle = <&pmu_system_controller>;
320 samsung,cluster-index = <0>;
324 compatible = "samsung,exynosautov920-wdt";
328 clock-names = "watchdog", "watchdog_src";
329 samsung,syscon-phandle = <&pmu_system_controller>;
330 samsung,cluster-index = <1>;
333 gic: interrupt-controller@10400000 {
334 compatible = "arm,gic-v3";
335 #interrupt-cells = <3>;
336 #address-cells = <0>;
337 interrupt-controller;
343 spdma0: dma-controller@10180000 {
348 clock-names = "apb_pclk";
349 #dma-cells = <1>;
352 spdma1: dma-controller@10190000 {
357 clock-names = "apb_pclk";
358 #dma-cells = <1>;
361 pdma0: dma-controller@101a0000 {
366 clock-names = "apb_pclk";
367 #dma-cells = <1>;
370 pdma1: dma-controller@101b0000 {
375 clock-names = "apb_pclk";
376 #dma-cells = <1>;
379 pdma2: dma-controller@101c0000 {
384 clock-names = "apb_pclk";
385 #dma-cells = <1>;
388 pdma3: dma-controller@101d0000 {
393 clock-names = "apb_pclk";
394 #dma-cells = <1>;
397 pdma4: dma-controller@101e0000 {
402 clock-names = "apb_pclk";
403 #dma-cells = <1>;
406 cmu_peric0: clock-controller@10800000 {
407 compatible = "samsung,exynosautov920-cmu-peric0";
409 #clock-cells = <1>;
414 clock-names = "oscclk",
420 compatible = "samsung,exynosautov920-peric0-sysreg",
426 compatible = "samsung,exynosautov920-pinctrl";
432 compatible = "samsung,exynosautov920-usi",
433 "samsung,exynos850-usi";
437 #address-cells = <1>;
438 #size-cells = <1>;
442 clock-names = "pclk", "ipclk";
446 compatible = "samsung,exynosautov920-uart",
447 "samsung,exynos850-uart";
450 pinctrl-names = "default";
451 pinctrl-0 = <&uart0_bus>;
454 clock-names = "uart", "clk_uart_baud0";
455 samsung,uart-fifosize = <256>;
460 compatible = "samsung,exynosautov920-spi",
461 "samsung,exynos850-spi";
464 pinctrl-names = "default";
465 pinctrl-0 = <&spi0_bus &spi0_cs_func>;
468 clock-names = "spi", "spi_busclk0";
469 samsung,spi-src-clk = <0>;
471 dma-names = "tx", "rx";
472 num-cs = <1>;
473 #address-cells = <1>;
474 #size-cells = <0>;
475 fifo-depth = <256>;
481 compatible = "samsung,exynosautov920-usi",
482 "samsung,exynos850-usi";
486 #address-cells = <1>;
487 #size-cells = <1>;
491 clock-names = "pclk", "ipclk";
495 compatible = "samsung,exynosautov920-uart",
496 "samsung,exynos850-uart";
499 pinctrl-names = "default";
500 pinctrl-0 = <&uart1_bus>;
503 clock-names = "uart", "clk_uart_baud0";
504 samsung,uart-fifosize = <256>;
509 compatible = "samsung,exynosautov920-spi",
510 "samsung,exynos850-spi";
513 pinctrl-names = "default";
514 pinctrl-0 = <&spi1_bus &spi1_cs_func>;
517 clock-names = "spi", "spi_busclk0";
518 samsung,spi-src-clk = <0>;
520 dma-names = "tx", "rx";
521 num-cs = <1>;
522 #address-cells = <1>;
523 #size-cells = <0>;
524 fifo-depth = <256>;
530 compatible = "samsung,exynosautov920-usi",
531 "samsung,exynos850-usi";
535 #address-cells = <1>;
536 #size-cells = <1>;
540 clock-names = "pclk", "ipclk";
544 compatible = "samsung,exynosautov920-uart",
545 "samsung,exynos850-uart";
548 pinctrl-names = "default";
549 pinctrl-0 = <&uart2_bus>;
552 clock-names = "uart", "clk_uart_baud0";
553 samsung,uart-fifosize = <64>;
558 compatible = "samsung,exynosautov920-spi",
559 "samsung,exynos850-spi";
562 pinctrl-names = "default";
563 pinctrl-0 = <&spi2_bus &spi2_cs_func>;
566 clock-names = "spi", "spi_busclk0";
567 samsung,spi-src-clk = <0>;
569 dma-names = "tx", "rx";
570 num-cs = <1>;
571 #address-cells = <1>;
572 #size-cells = <0>;
573 fifo-depth = <64>;
579 compatible = "samsung,exynosautov920-usi",
580 "samsung,exynos850-usi";
584 #address-cells = <1>;
585 #size-cells = <1>;
589 clock-names = "pclk", "ipclk";
593 compatible = "samsung,exynosautov920-uart",
594 "samsung,exynos850-uart";
597 pinctrl-names = "default";
598 pinctrl-0 = <&uart3_bus>;
601 clock-names = "uart", "clk_uart_baud0";
602 samsung,uart-fifosize = <64>;
607 compatible = "samsung,exynosautov920-spi",
608 "samsung,exynos850-spi";
611 pinctrl-names = "default";
612 pinctrl-0 = <&spi3_bus &spi3_cs_func>;
615 clock-names = "spi", "spi_busclk0";
616 samsung,spi-src-clk = <0>;
618 dma-names = "tx", "rx";
619 num-cs = <1>;
620 #address-cells = <1>;
621 #size-cells = <0>;
622 fifo-depth = <64>;
628 compatible = "samsung,exynosautov920-usi",
629 "samsung,exynos850-usi";
633 #address-cells = <1>;
634 #size-cells = <1>;
638 clock-names = "pclk", "ipclk";
642 compatible = "samsung,exynosautov920-uart",
643 "samsung,exynos850-uart";
646 pinctrl-names = "default";
647 pinctrl-0 = <&uart4_bus>;
650 clock-names = "uart", "clk_uart_baud0";
651 samsung,uart-fifosize = <64>;
656 compatible = "samsung,exynosautov920-spi",
657 "samsung,exynos850-spi";
660 pinctrl-names = "default";
661 pinctrl-0 = <&spi4_bus &spi4_cs_func>;
664 clock-names = "spi", "spi_busclk0";
665 samsung,spi-src-clk = <0>;
667 dma-names = "tx", "rx";
668 num-cs = <1>;
669 #address-cells = <1>;
670 #size-cells = <0>;
671 fifo-depth = <64>;
677 compatible = "samsung,exynosautov920-usi",
678 "samsung,exynos850-usi";
682 #address-cells = <1>;
683 #size-cells = <1>;
687 clock-names = "pclk", "ipclk";
691 compatible = "samsung,exynosautov920-uart",
692 "samsung,exynos850-uart";
695 pinctrl-names = "default";
696 pinctrl-0 = <&uart5_bus>;
699 clock-names = "uart", "clk_uart_baud0";
700 samsung,uart-fifosize = <64>;
705 compatible = "samsung,exynosautov920-spi",
706 "samsung,exynos850-spi";
709 pinctrl-names = "default";
710 pinctrl-0 = <&spi5_bus &spi5_cs_func>;
713 clock-names = "spi", "spi_busclk0";
714 samsung,spi-src-clk = <0>;
716 dma-names = "tx", "rx";
717 num-cs = <1>;
718 #address-cells = <1>;
719 #size-cells = <0>;
720 fifo-depth = <64>;
726 compatible = "samsung,exynosautov920-usi",
727 "samsung,exynos850-usi";
731 #address-cells = <1>;
732 #size-cells = <1>;
736 clock-names = "pclk", "ipclk";
740 compatible = "samsung,exynosautov920-uart",
741 "samsung,exynos850-uart";
744 pinctrl-names = "default";
745 pinctrl-0 = <&uart6_bus>;
748 clock-names = "uart", "clk_uart_baud0";
749 samsung,uart-fifosize = <64>;
754 compatible = "samsung,exynosautov920-spi",
755 "samsung,exynos850-spi";
758 pinctrl-names = "default";
759 pinctrl-0 = <&spi6_bus &spi6_cs_func>;
762 clock-names = "spi", "spi_busclk0";
763 samsung,spi-src-clk = <0>;
765 dma-names = "tx", "rx";
766 num-cs = <1>;
767 #address-cells = <1>;
768 #size-cells = <0>;
769 fifo-depth = <64>;
775 compatible = "samsung,exynosautov920-usi",
776 "samsung,exynos850-usi";
780 #address-cells = <1>;
781 #size-cells = <1>;
785 clock-names = "pclk", "ipclk";
789 compatible = "samsung,exynosautov920-uart",
790 "samsung,exynos850-uart";
793 pinctrl-names = "default";
794 pinctrl-0 = <&uart7_bus>;
797 clock-names = "uart", "clk_uart_baud0";
798 samsung,uart-fifosize = <64>;
803 compatible = "samsung,exynosautov920-spi",
804 "samsung,exynos850-spi";
807 pinctrl-names = "default";
808 pinctrl-0 = <&spi7_bus &spi7_cs_func>;
811 clock-names = "spi", "spi_busclk0";
812 samsung,spi-src-clk = <0>;
814 dma-names = "tx", "rx";
815 num-cs = <1>;
816 #address-cells = <1>;
817 #size-cells = <0>;
818 fifo-depth = <64>;
824 compatible = "samsung,exynosautov920-usi",
825 "samsung,exynos850-usi";
829 #address-cells = <1>;
830 #size-cells = <1>;
834 clock-names = "pclk", "ipclk";
838 compatible = "samsung,exynosautov920-uart",
839 "samsung,exynos850-uart";
842 pinctrl-names = "default";
843 pinctrl-0 = <&uart8_bus>;
846 clock-names = "uart", "clk_uart_baud0";
847 samsung,uart-fifosize = <64>;
852 compatible = "samsung,exynosautov920-spi",
853 "samsung,exynos850-spi";
856 pinctrl-names = "default";
857 pinctrl-0 = <&spi8_bus &spi8_cs_func>;
860 clock-names = "spi", "spi_busclk0";
861 samsung,spi-src-clk = <0>;
863 dma-names = "tx", "rx";
864 num-cs = <1>;
865 #address-cells = <1>;
866 #size-cells = <0>;
867 fifo-depth = <64>;
874 compatible = "samsung,exynosautov920-pwm",
875 "samsung,exynos4210-pwm";
877 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
878 #pwm-cells = <3>;
880 clock-names = "timers";
884 cmu_peric1: clock-controller@10c00000 {
885 compatible = "samsung,exynosautov920-cmu-peric1";
887 #clock-cells = <1>;
892 clock-names = "oscclk",
898 compatible = "samsung,exynosautov920-peric1-sysreg",
904 compatible = "samsung,exynosautov920-pinctrl";
910 compatible = "samsung,exynosautov920-usi",
911 "samsung,exynos850-usi";
915 #address-cells = <1>;
916 #size-cells = <1>;
920 clock-names = "pclk", "ipclk";
924 compatible = "samsung,exynosautov920-uart",
925 "samsung,exynos850-uart";
928 pinctrl-names = "default";
929 pinctrl-0 = <&uart9_bus>;
932 clock-names = "uart", "clk_uart_baud0";
933 samsung,uart-fifosize = <256>;
938 compatible = "samsung,exynosautov920-spi",
939 "samsung,exynos850-spi";
942 pinctrl-names = "default";
943 pinctrl-0 = <&spi9_bus &spi9_cs_func>;
946 clock-names = "spi", "spi_busclk0";
947 samsung,spi-src-clk = <0>;
949 dma-names = "tx", "rx";
950 num-cs = <1>;
951 #address-cells = <1>;
952 #size-cells = <0>;
953 fifo-depth = <256>;
959 compatible = "samsung,exynosautov920-usi",
960 "samsung,exynos850-usi";
964 #address-cells = <1>;
965 #size-cells = <1>;
969 clock-names = "pclk", "ipclk";
973 compatible = "samsung,exynosautov920-uart",
974 "samsung,exynos850-uart";
977 pinctrl-names = "default";
978 pinctrl-0 = <&uart10_bus>;
981 clock-names = "uart", "clk_uart_baud0";
982 samsung,uart-fifosize = <64>;
987 compatible = "samsung,exynosautov920-spi",
988 "samsung,exynos850-spi";
991 pinctrl-names = "default";
992 pinctrl-0 = <&spi10_bus &spi10_cs_func>;
995 clock-names = "spi", "spi_busclk0";
996 samsung,spi-src-clk = <0>;
998 dma-names = "tx", "rx";
999 num-cs = <1>;
1000 #address-cells = <1>;
1001 #size-cells = <0>;
1002 fifo-depth = <64>;
1008 compatible = "samsung,exynosautov920-usi",
1009 "samsung,exynos850-usi";
1013 #address-cells = <1>;
1014 #size-cells = <1>;
1018 clock-names = "pclk", "ipclk";
1022 compatible = "samsung,exynosautov920-uart",
1023 "samsung,exynos850-uart";
1026 pinctrl-names = "default";
1027 pinctrl-0 = <&uart11_bus>;
1030 clock-names = "uart", "clk_uart_baud0";
1031 samsung,uart-fifosize = <64>;
1036 compatible = "samsung,exynosautov920-spi",
1037 "samsung,exynos850-spi";
1040 pinctrl-names = "default";
1041 pinctrl-0 = <&spi11_bus &spi11_cs_func>;
1044 clock-names = "spi", "spi_busclk0";
1045 samsung,spi-src-clk = <0>;
1047 dma-names = "tx", "rx";
1048 num-cs = <1>;
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1051 fifo-depth = <64>;
1057 compatible = "samsung,exynosautov920-usi",
1058 "samsung,exynos850-usi";
1062 #address-cells = <1>;
1063 #size-cells = <1>;
1067 clock-names = "pclk", "ipclk";
1071 compatible = "samsung,exynosautov920-uart",
1072 "samsung,exynos850-uart";
1075 pinctrl-names = "default";
1076 pinctrl-0 = <&uart12_bus>;
1079 clock-names = "uart", "clk_uart_baud0";
1080 samsung,uart-fifosize = <64>;
1085 compatible = "samsung,exynosautov920-spi",
1086 "samsung,exynos850-spi";
1089 pinctrl-names = "default";
1090 pinctrl-0 = <&spi12_bus &spi12_cs_func>;
1093 clock-names = "spi", "spi_busclk0";
1094 samsung,spi-src-clk = <0>;
1096 dma-names = "tx", "rx";
1097 num-cs = <1>;
1098 #address-cells = <1>;
1099 #size-cells = <0>;
1100 fifo-depth = <64>;
1106 compatible = "samsung,exynosautov920-usi",
1107 "samsung,exynos850-usi";
1111 #address-cells = <1>;
1112 #size-cells = <1>;
1116 clock-names = "pclk", "ipclk";
1120 compatible = "samsung,exynosautov920-uart",
1121 "samsung,exynos850-uart";
1124 pinctrl-names = "default";
1125 pinctrl-0 = <&uart13_bus>;
1128 clock-names = "uart", "clk_uart_baud0";
1129 samsung,uart-fifosize = <64>;
1134 compatible = "samsung,exynosautov920-spi",
1135 "samsung,exynos850-spi";
1138 pinctrl-names = "default";
1139 pinctrl-0 = <&spi13_bus &spi13_cs_func>;
1142 clock-names = "spi", "spi_busclk0";
1143 samsung,spi-src-clk = <0>;
1145 dma-names = "tx", "rx";
1146 num-cs = <1>;
1147 #address-cells = <1>;
1148 #size-cells = <0>;
1149 fifo-depth = <64>;
1155 compatible = "samsung,exynosautov920-usi",
1156 "samsung,exynos850-usi";
1160 #address-cells = <1>;
1161 #size-cells = <1>;
1165 clock-names = "pclk", "ipclk";
1169 compatible = "samsung,exynosautov920-uart",
1170 "samsung,exynos850-uart";
1173 pinctrl-names = "default";
1174 pinctrl-0 = <&uart14_bus>;
1177 clock-names = "uart", "clk_uart_baud0";
1178 samsung,uart-fifosize = <64>;
1183 compatible = "samsung,exynosautov920-spi",
1184 "samsung,exynos850-spi";
1187 pinctrl-names = "default";
1188 pinctrl-0 = <&spi14_bus &spi14_cs_func>;
1191 clock-names = "spi", "spi_busclk0";
1192 samsung,spi-src-clk = <0>;
1194 dma-names = "tx", "rx";
1195 num-cs = <1>;
1196 #address-cells = <1>;
1197 #size-cells = <0>;
1198 fifo-depth = <64>;
1204 compatible = "samsung,exynosautov920-usi",
1205 "samsung,exynos850-usi";
1209 #address-cells = <1>;
1210 #size-cells = <1>;
1214 clock-names = "pclk", "ipclk";
1218 compatible = "samsung,exynosautov920-uart",
1219 "samsung,exynos850-uart";
1222 pinctrl-names = "default";
1223 pinctrl-0 = <&uart15_bus>;
1226 clock-names = "uart", "clk_uart_baud0";
1227 samsung,uart-fifosize = <64>;
1232 compatible = "samsung,exynosautov920-spi",
1233 "samsung,exynos850-spi";
1236 pinctrl-names = "default";
1237 pinctrl-0 = <&spi15_bus &spi15_cs_func>;
1240 clock-names = "spi", "spi_busclk0";
1241 samsung,spi-src-clk = <0>;
1243 dma-names = "tx", "rx";
1244 num-cs = <1>;
1245 #address-cells = <1>;
1246 #size-cells = <0>;
1247 fifo-depth = <64>;
1253 compatible = "samsung,exynosautov920-usi",
1254 "samsung,exynos850-usi";
1258 #address-cells = <1>;
1259 #size-cells = <1>;
1263 clock-names = "pclk", "ipclk";
1267 compatible = "samsung,exynosautov920-uart",
1268 "samsung,exynos850-uart";
1271 pinctrl-names = "default";
1272 pinctrl-0 = <&uart16_bus>;
1275 clock-names = "uart", "clk_uart_baud0";
1276 samsung,uart-fifosize = <64>;
1281 compatible = "samsung,exynosautov920-spi",
1282 "samsung,exynos850-spi";
1285 pinctrl-names = "default";
1286 pinctrl-0 = <&spi16_bus &spi16_cs_func>;
1289 clock-names = "spi", "spi_busclk0";
1290 samsung,spi-src-clk = <0>;
1292 dma-names = "tx", "rx";
1293 num-cs = <1>;
1294 #address-cells = <1>;
1295 #size-cells = <0>;
1296 fifo-depth = <64>;
1302 compatible = "samsung,exynosautov920-usi",
1303 "samsung,exynos850-usi";
1307 #address-cells = <1>;
1308 #size-cells = <1>;
1312 clock-names = "pclk", "ipclk";
1316 compatible = "samsung,exynosautov920-uart",
1317 "samsung,exynos850-uart";
1320 pinctrl-names = "default";
1321 pinctrl-0 = <&uart17_bus>;
1324 clock-names = "uart", "clk_uart_baud0";
1325 samsung,uart-fifosize = <64>;
1330 compatible = "samsung,exynosautov920-spi",
1331 "samsung,exynos850-spi";
1334 pinctrl-names = "default";
1335 pinctrl-0 = <&spi17_bus &spi17_cs_func>;
1338 clock-names = "spi", "spi_busclk0";
1339 samsung,spi-src-clk = <0>;
1341 dma-names = "tx", "rx";
1342 num-cs = <1>;
1343 #address-cells = <1>;
1344 #size-cells = <0>;
1345 fifo-depth = <64>;
1350 cmu_top: clock-controller@11000000 {
1351 compatible = "samsung,exynosautov920-cmu-top";
1353 #clock-cells = <1>;
1356 clock-names = "oscclk";
1360 compatible = "samsung,exynosautov920-pinctrl";
1363 wakeup-interrupt-controller {
1364 compatible = "samsung,exynosautov920-wakeup-eint";
1368 pmu_system_controller: system-controller@11860000 {
1369 compatible = "samsung,exynosautov920-pmu",
1370 "samsung,exynos7-pmu","syscon";
1374 cmu_hsi0: clock-controller@16000000 {
1375 compatible = "samsung,exynosautov920-cmu-hsi0";
1377 #clock-cells = <1>;
1381 clock-names = "oscclk",
1386 compatible = "samsung,exynosautov920-pinctrl";
1391 cmu_hsi1: clock-controller@16400000 {
1392 compatible = "samsung,exynosautov920-cmu-hsi1";
1394 #clock-cells = <1>;
1400 clock-names = "oscclk",
1407 compatible = "samsung,exynosautov920-pinctrl";
1412 cmu_hsi2: clock-controller@16b00000 {
1413 compatible = "samsung,exynosautov920-cmu-hsi2";
1415 #clock-cells = <1>;
1422 clock-names = "oscclk",
1430 compatible = "samsung,exynosautov920-pinctrl";
1436 compatible = "samsung,exynosautov920-pinctrl";
1442 compatible = "samsung,exynosautov920-ufs-phy";
1444 reg-names = "phy-pma";
1446 clock-names = "ref_clk";
1447 samsung,pmu-syscon = <&pmu_system_controller>;
1448 #phy-cells = <0>;
1453 compatible = "samsung,exynosautov920-pinctrl";
1457 cmu_cpucl0: clock-controller@1ec00000 {
1458 compatible = "samsung,exynosautov920-cmu-cpucl0";
1460 #clock-cells = <1>;
1466 clock-names = "oscclk",
1472 cmu_cpucl1: clock-controller@1ed00000 {
1473 compatible = "samsung,exynosautov920-cmu-cpucl1";
1475 #clock-cells = <1>;
1480 clock-names = "oscclk",
1485 cmu_cpucl2: clock-controller@1ee00000 {
1486 compatible = "samsung,exynosautov920-cmu-cpucl2";
1488 #clock-cells = <1>;
1493 clock-names = "oscclk",
1500 compatible = "arm,armv8-timer";
1509 #include "exynosautov920-pinctrl.dtsi"