Lines Matching +full:0 +full:x13400000
52 #size-cells = <0>;
89 reg = <0x100>;
96 reg = <0x101>;
103 reg = <0x102>;
110 reg = <0x103>;
117 reg = <0x200>;
124 reg = <0x201>;
128 cpu6: cpu@0 {
131 reg = <0x0>;
138 reg = <0x1>;
146 cpu_suspend = <0xc4000001>;
147 cpu_off = <0x84000002>;
148 cpu_on = <0xc4000003>;
163 #clock-cells = <0>;
168 soc: soc@0 {
172 ranges = <0x0 0x0 0x0 0x20000000>;
177 reg = <0x10000000 0x24>;
183 #address-cells = <0>;
185 reg = <0x12301000 0x1000>,
186 <0x12302000 0x2000>,
187 <0x12304000 0x2000>,
188 <0x12306000 0x2000>;
195 reg = <0x10010000 0x8000>;
222 reg = <0x12000000 0x8000>;
237 reg = <0x12060000 0x8000>;
246 reg = <0x13400000 0x8000>;
265 reg = <0x11cb0000 0x1000>;
277 reg = <0x13430000 0x1000>;
283 reg = <0x139b0000 0x1000>;
289 reg = <0x148f0000 0x1000>;
296 reg = <0x11c80000 0x10000>;
302 reg = <0x13500000 0x2000>;
305 #size-cells = <0>;
309 fifo-depth = <0x40>;
316 reg = <0x13800000 0x100>;
319 pinctrl-0 = <&uart0_bus>;
330 reg = <0x13810000 0x100>;
333 pinctrl-0 = <&uart1_bus>;
344 reg = <0x13820000 0x100>;
347 pinctrl-0 = <&uart2_bus>;
358 reg = <0x13830000 0x100>;
361 #size-cells = <0>;
363 pinctrl-0 = <&i2c0_bus>;
372 reg = <0x13840000 0x100>;
375 #size-cells = <0>;
377 pinctrl-0 = <&i2c1_bus>;
386 reg = <0x13850000 0x100>;
389 #size-cells = <0>;
391 pinctrl-0 = <&i2c2_bus>;
400 reg = <0x13860000 0x100>;
403 #size-cells = <0>;
405 pinctrl-0 = <&i2c3_bus>;
414 reg = <0x13870000 0x100>;
417 #size-cells = <0>;
419 pinctrl-0 = <&i2c4_bus>;
428 reg = <0x13880000 0x100>;
431 #size-cells = <0>;
433 pinctrl-0 = <&i2c5_bus>;
442 reg = <0x13890000 0x100>;
445 #size-cells = <0>;
447 pinctrl-0 = <&i2c6_bus>;
456 reg = <0x11cd0000 0x100>;
459 #size-cells = <0>;
461 pinctrl-0 = <&i2c7_bus>;