Lines Matching +full:0 +full:x02020000
21 #address-cells = <0x2>;
22 #size-cells = <0x0>;
24 cpu@0 {
27 reg = <0x0 0x0>;
34 reg = <0x0 0x1>;
41 reg = <0x0 0x2>;
48 reg = <0x0 0x3>;
66 reg = <0x04 0x00080000 0x0 0x20000>, /* GICD */
67 <0x04 0x01000000 0x0 0x1000000>; /* GICR */
73 reg = <0x04 0x00100000 0x0 0x20000>; /* GIC ITS */
92 #clock-cells = <0>;
104 /* ECAM at 0x3000_0000 - 0x4000_0000 */
105 reg = <0x0 0x30000000 0x0 0x10000000>;
110 * MEM 0x4000_0000 - 0x6000_0000
111 * MEM64 pref 0x40_0000_0000 - 0x60_0000_0000
114 <0x02000000 0 0x40000000 0 0x40000000 0 0x20000000
115 0x43000000 0x40 0x00000000 0x40 0x00000000 0x20 0x00000000>;
116 bus-range = <0 0xff>;
117 interrupt-map-mask = <0 0 0 7>;
120 <0 0 0 1 &gic 0 0 GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
121 0 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
122 0 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
123 0 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
136 reg = <0x04 0x02020000 0x0 0x1000>;