Lines Matching +full:0 +full:x10e
63 #size-cells = <0>;
65 cpu@0 {
68 reg = <0x0 0x000>;
74 reg = <0x0 0x001>;
80 reg = <0x0 0x002>;
86 reg = <0x0 0x003>;
92 reg = <0x0 0x004>;
98 reg = <0x0 0x005>;
104 reg = <0x0 0x006>;
110 reg = <0x0 0x007>;
116 reg = <0x0 0x008>;
122 reg = <0x0 0x009>;
128 reg = <0x0 0x00a>;
134 reg = <0x0 0x00b>;
140 reg = <0x0 0x00c>;
146 reg = <0x0 0x00d>;
152 reg = <0x0 0x00e>;
158 reg = <0x0 0x00f>;
164 reg = <0x0 0x100>;
170 reg = <0x0 0x101>;
176 reg = <0x0 0x102>;
182 reg = <0x0 0x103>;
188 reg = <0x0 0x104>;
194 reg = <0x0 0x105>;
200 reg = <0x0 0x106>;
206 reg = <0x0 0x107>;
212 reg = <0x0 0x108>;
218 reg = <0x0 0x109>;
224 reg = <0x0 0x10a>;
230 reg = <0x0 0x10b>;
236 reg = <0x0 0x10c>;
242 reg = <0x0 0x10d>;
248 reg = <0x0 0x10e>;
254 reg = <0x0 0x10f>;
260 reg = <0x0 0x200>;
266 reg = <0x0 0x201>;
272 reg = <0x0 0x202>;
278 reg = <0x0 0x203>;
284 reg = <0x0 0x204>;
290 reg = <0x0 0x205>;
296 reg = <0x0 0x206>;
302 reg = <0x0 0x207>;
308 reg = <0x0 0x208>;
314 reg = <0x0 0x209>;
320 reg = <0x0 0x20a>;
326 reg = <0x0 0x20b>;
332 reg = <0x0 0x20c>;
338 reg = <0x0 0x20d>;
344 reg = <0x0 0x20e>;
350 reg = <0x0 0x20f>;
370 #clock-cells = <0>;
388 reg = <0x8010 0x00000000 0x0 0x010000>, /* GICD */
389 <0x8010 0x80000000 0x0 0x600000>; /* GICR */
390 interrupts = <1 9 0xf04>;
396 reg = <0x8010 0x20000 0x0 0x200000>;
402 reg = <0x87e0 0x24000000 0x0 0x1000>;
410 reg = <0x87e0 0x25000000 0x0 0x1000>;