Lines Matching +full:nand +full:- +full:cache
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #address-cells = <2>;
13 #size-cells = <2>;
15 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <0>;
22 compatible = "brcm,brahma-b53";
25 next-level-cache = <&L2_0>;
26 enable-method = "psci";
30 compatible = "brcm,brahma-b53";
33 next-level-cache = <&L2_0>;
34 enable-method = "psci";
38 compatible = "brcm,brahma-b53";
41 next-level-cache = <&L2_0>;
42 enable-method = "psci";
46 compatible = "brcm,brahma-b53";
49 next-level-cache = <&L2_0>;
50 enable-method = "psci";
53 L2_0: l2-cache0 {
54 compatible = "cache";
55 cache-level = <2>;
56 cache-unified;
61 compatible = "arm,armv8-timer";
69 compatible = "arm,cortex-a53-pmu";
74 interrupt-affinity = <&B53_0>, <&B53_1>,
79 periph_clk: periph-clk {
80 compatible = "fixed-clock";
81 #clock-cells = <0>;
82 clock-frequency = <200000000>;
85 uart_clk: uart-clk {
86 compatible = "fixed-factor-clock";
87 #clock-cells = <0>;
89 clock-div = <4>;
90 clock-mult = <1>;
93 hsspi_pll: hsspi-pll {
94 compatible = "fixed-clock";
95 #clock-cells = <0>;
96 clock-frequency = <400000000>;
101 compatible = "arm,psci-0.2";
106 compatible = "simple-bus";
107 #address-cells = <1>;
108 #size-cells = <1>;
111 gic: interrupt-controller@1000 {
112 compatible = "arm,gic-400";
113 #interrupt-cells = <3>;
114 interrupt-controller;
124 compatible = "simple-bus";
125 #address-cells = <1>;
126 #size-cells = <1>;
131 compatible = "brcm,bcm6345-gpio";
133 reg-names = "dirout", "dat";
134 gpio-controller;
135 #gpio-cells = <2>;
141 compatible = "brcm,bcm6345-gpio";
143 reg-names = "dirout", "dat";
144 gpio-controller;
145 #gpio-cells = <2>;
151 compatible = "brcm,bcm6345-gpio";
153 reg-names = "dirout", "dat";
154 gpio-controller;
155 #gpio-cells = <2>;
161 compatible = "brcm,bcm6345-gpio";
163 reg-names = "dirout", "dat";
164 gpio-controller;
165 #gpio-cells = <2>;
171 compatible = "brcm,bcm6345-gpio";
173 reg-names = "dirout", "dat";
174 gpio-controller;
175 #gpio-cells = <2>;
181 compatible = "brcm,bcm6345-gpio";
183 reg-names = "dirout", "dat";
184 gpio-controller;
185 #gpio-cells = <2>;
191 compatible = "brcm,bcm6345-gpio";
193 reg-names = "dirout", "dat";
194 gpio-controller;
195 #gpio-cells = <2>;
201 compatible = "brcm,bcm6345-gpio";
203 reg-names = "dirout", "dat";
204 gpio-controller;
205 #gpio-cells = <2>;
210 leds: led-controller@800 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 compatible = "brcm,bcm63138-leds";
219 compatible = "brcm,iproc-rng200";
225 #address-cells = <1>;
226 #size-cells = <0>;
227 compatible = "brcm,bcm63158-hsspi", "brcm,bcmbca-hsspi-v1.0";
231 clock-names = "hsspi", "pll";
232 num-cs = <8>;
236 nand_controller: nand-controller@1800 {
237 #address-cells = <1>;
238 #size-cells = <0>;
239 compatible = "brcm,nand-bcm63138", "brcm,brcmnand-v7.1", "brcm,brcmnand";
241 reg-names = "nand", "nand-int-base";
244 nandcs: nand@0 {
251 pl081_dma: dma-controller@11000 {
254 arm,primecell-periphid = <0x00041081>;
257 memcpy-burst-size = <256>;
258 memcpy-bus-width = <32>;
260 clock-names = "apb_pclk";
261 #dma-cells = <2>;
270 clock-names = "uartclk", "apb_pclk";
279 clock-names = "uartclk", "apb_pclk";
288 clock-names = "uartclk", "apb_pclk";