Lines Matching +full:i +full:- +full:cache +full:- +full:sets
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #address-cells = <2>;
8 #size-cells = <2>;
10 interrupt-parent = <&gicv2>;
14 clk_osc: clk-osc {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-output-names = "osc";
18 clock-frequency = <54000000>;
21 clk_vpu: clk-vpu {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <750000000>;
25 clock-output-names = "vpu-clock";
28 clk_uart: clk-uart {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <9216000>;
32 clock-output-names = "uart-clock";
35 clk_emmc2: clk-emmc2 {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <200000000>;
39 clock-output-names = "emmc2-clock";
44 #address-cells = <1>;
45 #size-cells = <0>;
47 /* Source for L1 d/i cache-line-size, cache-sets, cache-size
48 …* https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?…
49 * Source for L2 cache-line-size and cache-sets:
50 …* https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?…
51 * and for cache-size:
56 compatible = "arm,cortex-a76";
58 enable-method = "psci";
59 d-cache-size = <0x10000>;
60 d-cache-line-size = <64>;
61 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
62 i-cache-size = <0x10000>;
63 i-cache-line-size = <64>;
64 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
65 next-level-cache = <&l2_cache_l0>;
67 l2_cache_l0: l2-cache-l0 {
68 compatible = "cache";
69 cache-size = <0x80000>;
70 cache-line-size = <64>;
71 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
72 cache-level = <2>;
73 cache-unified;
74 next-level-cache = <&l3_cache>;
80 compatible = "arm,cortex-a76";
82 enable-method = "psci";
83 d-cache-size = <0x10000>;
84 d-cache-line-size = <64>;
85 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
86 i-cache-size = <0x10000>;
87 i-cache-line-size = <64>;
88 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
89 next-level-cache = <&l2_cache_l1>;
91 l2_cache_l1: l2-cache-l1 {
92 compatible = "cache";
93 cache-size = <0x80000>;
94 cache-line-size = <64>;
95 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
96 cache-level = <2>;
97 cache-unified;
98 next-level-cache = <&l3_cache>;
104 compatible = "arm,cortex-a76";
106 enable-method = "psci";
107 d-cache-size = <0x10000>;
108 d-cache-line-size = <64>;
109 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
110 i-cache-size = <0x10000>;
111 i-cache-line-size = <64>;
112 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
113 next-level-cache = <&l2_cache_l2>;
115 l2_cache_l2: l2-cache-l2 {
116 compatible = "cache";
117 cache-size = <0x80000>;
118 cache-line-size = <64>;
119 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
120 cache-level = <2>;
121 cache-unified;
122 next-level-cache = <&l3_cache>;
128 compatible = "arm,cortex-a76";
130 enable-method = "psci";
131 d-cache-size = <0x10000>;
132 d-cache-line-size = <64>;
133 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
134 i-cache-size = <0x10000>;
135 i-cache-line-size = <64>;
136 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
137 next-level-cache = <&l2_cache_l3>;
139 l2_cache_l3: l2-cache-l3 {
140 compatible = "cache";
141 cache-size = <0x80000>;
142 cache-line-size = <64>;
143 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
144 cache-level = <2>;
145 cache-unified;
146 next-level-cache = <&l3_cache>;
150 /* Source for cache-line-size and cache-sets:
151 * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en
152 * Source for cache-size:
155 l3_cache: l3-cache {
156 compatible = "cache";
157 cache-size = <0x200000>;
158 cache-line-size = <64>;
159 cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set
160 cache-level = <3>;
161 cache-unified;
167 compatible = "arm,psci-1.0", "arm,psci-0.2";
170 rmem: reserved-memory {
172 #address-cells = <2>;
173 #size-cells = <2>;
177 no-map;
181 compatible = "shared-dma-pool";
184 linux,cma-default;
185 alloc-ranges = <0x0 0x00000000 0x0 0x40000000>;
190 compatible = "simple-bus";
192 #address-cells = <1>;
193 #size-cells = <1>;
196 compatible = "brcm,bcm2712-sdhci",
197 "brcm,sdhci-brcmstb";
200 reg-names = "host", "cfg";
203 clock-names = "sw_sdio";
204 mmc-ddr-3_3v;
208 compatible = "brcm,bcm2835-system-timer";
214 clock-frequency = <1000000>;
218 compatible = "brcm,bcm2835-mbox";
221 #mbox-cells = <0>;
224 local_intc: interrupt-controller@7cd00000 {
225 compatible = "brcm,bcm2836-l1-intc";
234 clock-names = "uartclk", "apb_pclk";
235 arm,primecell-periphid = <0x00241011>;
239 interrupt-controller@7d517000 {
240 compatible = "brcm,bcm7271-l2-intc";
243 interrupt-controller;
244 #interrupt-cells = <1>;
248 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
250 gpio-controller;
251 #gpio-cells = <2>;
252 brcm,gpio-bank-widths = <17 6>;
253 /* The lack of 'interrupt-controller' property here is intended:
259 gicv2: interrupt-controller@7fff9000 {
260 compatible = "arm,gic-400";
265 interrupt-controller;
266 #interrupt-cells = <3>;
271 compatible = "arm,armv8-timer";