Lines Matching +full:cache +full:- +full:controller +full:- +full:0
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #address-cells = <2>;
8 #size-cells = <2>;
10 interrupt-parent = <&gicv2>;
14 clk_osc: clk-osc {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-output-names = "osc";
18 clock-frequency = <54000000>;
21 clk_vpu: clk-vpu {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <750000000>;
25 clock-output-names = "vpu-clock";
28 clk_uart: clk-uart {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <9216000>;
32 clock-output-names = "uart-clock";
35 clk_emmc2: clk-emmc2 {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <200000000>;
39 clock-output-names = "emmc2-clock";
42 clk_sw_baud: clk-sw-baud {
43 compatible = "fixed-clock";
44 #clock-cells = <0>;
45 clock-frequency = <96000000>;
46 clock-output-names = "sw-baud";
51 #address-cells = <1>;
52 #size-cells = <0>;
54 /* Source for L1 d/i cache-line-size, cache-sets, cache-size
55 …* https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?…
56 * Source for L2 cache-line-size and cache-sets:
57 …* https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?…
58 * and for cache-size:
61 cpu0: cpu@0 {
63 compatible = "arm,cortex-a76";
64 reg = <0x000>;
65 enable-method = "psci";
66 d-cache-size = <0x10000>;
67 d-cache-line-size = <64>;
68 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
69 i-cache-size = <0x10000>;
70 i-cache-line-size = <64>;
71 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
72 next-level-cache = <&l2_cache_l0>;
74 l2_cache_l0: l2-cache {
75 compatible = "cache";
76 cache-size = <0x80000>;
77 cache-line-size = <64>;
78 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
79 cache-level = <2>;
80 cache-unified;
81 next-level-cache = <&l3_cache>;
87 compatible = "arm,cortex-a76";
88 reg = <0x100>;
89 enable-method = "psci";
90 d-cache-size = <0x10000>;
91 d-cache-line-size = <64>;
92 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
93 i-cache-size = <0x10000>;
94 i-cache-line-size = <64>;
95 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
96 next-level-cache = <&l2_cache_l1>;
98 l2_cache_l1: l2-cache {
99 compatible = "cache";
100 cache-size = <0x80000>;
101 cache-line-size = <64>;
102 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
103 cache-level = <2>;
104 cache-unified;
105 next-level-cache = <&l3_cache>;
111 compatible = "arm,cortex-a76";
112 reg = <0x200>;
113 enable-method = "psci";
114 d-cache-size = <0x10000>;
115 d-cache-line-size = <64>;
116 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
117 i-cache-size = <0x10000>;
118 i-cache-line-size = <64>;
119 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
120 next-level-cache = <&l2_cache_l2>;
122 l2_cache_l2: l2-cache {
123 compatible = "cache";
124 cache-size = <0x80000>;
125 cache-line-size = <64>;
126 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
127 cache-level = <2>;
128 cache-unified;
129 next-level-cache = <&l3_cache>;
135 compatible = "arm,cortex-a76";
136 reg = <0x300>;
137 enable-method = "psci";
138 d-cache-size = <0x10000>;
139 d-cache-line-size = <64>;
140 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
141 i-cache-size = <0x10000>;
142 i-cache-line-size = <64>;
143 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
144 next-level-cache = <&l2_cache_l3>;
146 l2_cache_l3: l2-cache {
147 compatible = "cache";
148 cache-size = <0x80000>;
149 cache-line-size = <64>;
150 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
151 cache-level = <2>;
152 cache-unified;
153 next-level-cache = <&l3_cache>;
157 /* Source for cache-line-size and cache-sets:
158 * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en
159 * Source for cache-size:
162 l3_cache: l3-cache {
163 compatible = "cache";
164 cache-size = <0x200000>;
165 cache-line-size = <64>;
166 cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set
167 cache-level = <3>;
168 cache-unified;
174 compatible = "arm,psci-1.0", "arm,psci-0.2";
177 rmem: reserved-memory {
179 #address-cells = <2>;
180 #size-cells = <2>;
182 atf@0 {
183 reg = <0x0 0x0 0x0 0x80000>;
184 no-map;
188 compatible = "shared-dma-pool";
189 size = <0x0 0x4000000>; /* 64MB */
191 linux,cma-default;
192 alloc-ranges = <0x0 0x00000000 0x0 0x40000000>;
197 compatible = "simple-bus";
198 ranges = <0x00000000 0x10 0x00000000 0x80000000>;
199 #address-cells = <1>;
200 #size-cells = <1>;
202 pcie_rescal: reset-controller@119500 {
203 compatible = "brcm,bcm7216-pcie-sata-rescal";
204 reg = <0x00119500 0x10>;
205 #reset-cells = <0>;
209 compatible = "brcm,bcm2712-sdhci",
210 "brcm,sdhci-brcmstb";
211 reg = <0x00fff000 0x260>,
212 <0x00fff400 0x200>;
213 reg-names = "host", "cfg";
216 clock-names = "sw_sdio";
217 mmc-ddr-3_3v;
220 bcm_reset: reset-controller@1504318 {
221 compatible = "brcm,brcmstb-reset";
222 reg = <0x01504318 0x30>;
223 #reset-cells = <1>;
227 compatible = "brcm,bcm2835-system-timer";
228 reg = <0x7c003000 0x1000>;
233 clock-frequency = <1000000>;
237 compatible = "brcm,bcm2835-mbox";
238 reg = <0x7c013880 0x40>;
240 #mbox-cells = <0>;
245 reg = <0x7d001000 0x200>;
248 clock-names = "uartclk", "apb_pclk";
249 arm,primecell-periphid = <0x00341011>;
254 compatible = "brcm,bcm2712c0-pinctrl";
255 reg = <0x7d504100 0x30>;
259 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
260 reg = <0x7d508500 0x40>;
261 interrupt-parent = <&main_irq>;
262 interrupts = <0>;
263 gpio-controller;
264 #gpio-cells = <2>;
265 interrupt-controller;
266 #interrupt-cells = <2>;
267 brcm,gpio-bank-widths = <32 22>;
271 compatible = "brcm,bcm7271-uart";
272 reg = <0x7d50c000 0x20>;
273 reg-names = "uart";
275 clock-names = "sw_baud";
277 interrupt-names = "uart";
282 compatible = "brcm,bcm2712c0-aon-pinctrl";
283 reg = <0x7d510700 0x20>;
286 interrupt-controller@7d517000 {
287 compatible = "brcm,bcm7271-l2-intc";
288 reg = <0x7d517000 0x10>;
290 interrupt-controller;
291 #interrupt-cells = <1>;
295 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
296 reg = <0x7d517c00 0x40>;
297 gpio-controller;
298 #gpio-cells = <2>;
299 brcm,gpio-bank-widths = <17 6>;
300 /* The lack of 'interrupt-controller' property here is intended:
301 * don't use GIO_AON as an interrupt controller because it will
307 compatible = "brcm,bcm2712-sdhci",
308 "brcm,sdhci-brcmstb";
309 reg = <0x01100000 0x260>,
310 <0x01100400 0x200>;
311 reg-names = "host", "cfg";
314 clock-names = "sw_sdio";
315 sdhci-caps-mask = <0x0000C000 0x0>;
316 sdhci-caps = <0x0 0x0>;
317 mmc-ddr-3_3v;
321 gicv2: interrupt-controller@7fff9000 {
322 compatible = "arm,gic-400";
323 reg = <0x7fff9000 0x1000>,
324 <0x7fffa000 0x2000>,
325 <0x7fffc000 0x2000>,
326 <0x7fffe000 0x2000>;
327 interrupt-controller;
328 #address-cells = <0>;
331 #interrupt-cells = <3>;
334 aon_intr: interrupt-controller@7d510600 {
335 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
336 reg = <0x7d510600 0x30>;
338 interrupt-controller;
339 #interrupt-cells = <1>;
343 compatible = "brcm,bcm2712-pixelvalve0";
344 reg = <0x7c410000 0x100>;
349 compatible = "brcm,bcm2712-pixelvalve1";
350 reg = <0x7c411000 0x100>;
355 compatible = "brcm,bcm2712-mop";
356 reg = <0x7c500000 0x28>;
357 interrupt-parent = <&disp_intr>;
362 compatible = "brcm,bcm2712-moplet";
363 reg = <0x7c501000 0x20>;
364 interrupt-parent = <&disp_intr>;
365 interrupts = <0>;
368 disp_intr: interrupt-controller@7c502000 {
369 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
370 reg = <0x7c502000 0x30>;
372 interrupt-controller;
373 #interrupt-cells = <1>;
377 compatible = "brcm,brcm2711-dvp";
378 reg = <0x7c700000 0x10>;
380 #clock-cells = <1>;
381 #reset-cells = <1>;
385 compatible = "brcm,brcmstb-i2c";
386 reg = <0x7d508200 0x58>;
387 interrupt-parent = <&bsc_irq>;
389 clock-frequency = <97500>;
390 #address-cells = <1>;
391 #size-cells = <0>;
395 compatible = "brcm,brcmstb-i2c";
396 reg = <0x7d508280 0x58>;
397 interrupt-parent = <&bsc_irq>;
399 clock-frequency = <97500>;
400 #address-cells = <1>;
401 #size-cells = <0>;
404 bsc_irq: interrupt-controller@7d508380 {
405 compatible = "brcm,bcm7271-l2-intc";
406 reg = <0x7d508380 0x10>;
408 interrupt-controller;
409 #interrupt-cells = <1>;
412 main_irq: interrupt-controller@7d508400 {
413 compatible = "brcm,bcm7271-l2-intc";
414 reg = <0x7d508400 0x10>;
416 interrupt-controller;
417 #interrupt-cells = <1>;
421 compatible = "brcm,bcm2712-hdmi0";
422 reg = <0x7c701400 0x300>,
423 <0x7c701000 0x200>,
424 <0x7c701d00 0x300>,
425 <0x7c702000 0x80>,
426 <0x7c703800 0x200>,
427 <0x7c704000 0x800>,
428 <0x7c700100 0x80>,
429 <0x7d510800 0x100>,
430 <0x7c720000 0x100>;
431 reg-names = "hdmi",
441 interrupt-parent = <&aon_intr>;
444 interrupt-names = "cec-tx", "cec-rx", "cec-low",
445 "hpd-connected", "hpd-removed";
450 compatible = "brcm,bcm2712-hdmi1";
451 reg = <0x7c706400 0x300>,
452 <0x7c706000 0x200>,
453 <0x7c706d00 0x300>,
454 <0x7c707000 0x80>,
455 <0x7c708800 0x200>,
456 <0x7c709000 0x800>,
457 <0x7c700180 0x80>,
458 <0x7d511000 0x100>,
459 <0x7c720000 0x100>;
460 reg-names = "hdmi",
470 interrupt-parent = <&aon_intr>;
473 interrupt-names = "cec-tx", "cec-rx", "cec-low",
474 "hpd-connected", "hpd-removed";
480 compatible = "simple-bus";
481 #address-cells = <2>;
482 #size-cells = <2>;
484 ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
485 <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
486 <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
487 <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
488 <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
490 dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
491 <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
492 <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
493 <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
494 <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
497 compatible = "brcm,bcm2712-vc6";
501 compatible = "brcm,bcm2712-pcie";
502 reg = <0x10 0x00100000 0x00 0x9310>;
504 linux,pci-domain = <0>;
505 max-link-speed = <2>;
506 num-lanes = <1>;
507 #address-cells = <3>;
508 #interrupt-cells = <1>;
509 #size-cells = <2>;
510 interrupt-parent = <&gicv2>;
513 interrupt-names = "pcie", "msi";
514 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
515 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
516 <0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
517 <0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
518 <0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
520 reset-names = "rescal", "bridge";
521 msi-controller;
522 msi-parent = <&pcie0>;
525 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
526 <0x02000000 0x00 0x00000000 0x17 0x00000000 0x00 0xfffffffc>,
527 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
528 <0x43000000 0x04 0x00000000 0x14 0x00000000 0x03 0x00000000>;
530 dma-ranges =
531 /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */
532 <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>;
538 compatible = "brcm,bcm2712-pcie";
539 reg = <0x10 0x00110000 0x00 0x9310>;
541 linux,pci-domain = <1>;
542 max-link-speed = <2>;
543 num-lanes = <1>;
544 #address-cells = <3>;
545 #interrupt-cells = <1>;
546 #size-cells = <2>;
547 interrupt-parent = <&gicv2>;
550 interrupt-names = "pcie", "msi";
551 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
552 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
553 <0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
554 <0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
555 <0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
557 reset-names = "rescal", "bridge";
558 msi-controller;
559 msi-parent = <&mip1>;
562 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
563 <0x02000000 0x00 0x00000000 0x1b 0x00000000 0x00 0xfffffffc>,
564 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
565 <0x43000000 0x04 0x00000000 0x18 0x00000000 0x03 0x00000000>;
567 dma-ranges =
568 /* 64GiB, 64-bit, non-prefetchable at PCIe 10_0000_0000 */
569 <0x03000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>,
570 /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP1 */
571 <0x03000000 0xff 0xfffff000 0x10 0x00131000 0x00 0x00001000>;
577 compatible = "brcm,bcm2712-pcie";
578 reg = <0x10 0x00120000 0x00 0x9310>;
580 linux,pci-domain = <2>;
581 max-link-speed = <2>;
582 num-lanes = <4>;
583 #address-cells = <3>;
584 #interrupt-cells = <1>;
585 #size-cells = <2>;
586 interrupt-parent = <&gicv2>;
589 interrupt-names = "pcie", "msi";
590 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
591 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
592 <0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
593 <0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
594 <0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
596 reset-names = "rescal", "bridge";
597 msi-controller;
598 msi-parent = <&mip0>;
601 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
602 <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0xfffffffc>,
603 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
604 <0x43000000 0x04 0x00000000 0x1c 0x00000000 0x03 0x00000000>;
606 dma-ranges =
607 /* 4MiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
608 <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0x00400000>,
609 /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */
610 <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>,
611 /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP0 */
612 <0x03000000 0xff 0xfffff000 0x10 0x00130000 0x00 0x00001000>;
617 mip0: msi-controller@1000130000 {
618 compatible = "brcm,bcm2712-mip";
619 reg = <0x10 0x00130000 0x00 0xc0>,
620 <0xff 0xfffff000 0x00 0x1000>;
621 msi-controller;
622 msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>;
623 brcm,msi-offset = <0>;
626 mip1: msi-controller@1000131000 {
627 compatible = "brcm,bcm2712-mip";
628 reg = <0x10 0x00131000 0x00 0xc0>,
629 <0xff 0xfffff000 0x00 0x1000>;
630 msi-controller;
631 msi-ranges = <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>;
632 brcm,msi-offset = <8>;
637 compatible = "arm,armv8-timer";
650 clk_27MHz: clk-27M {
651 #clock-cells = <0>;
652 compatible = "fixed-clock";
653 clock-frequency = <27000000>;
654 clock-output-names = "27MHz-clock";
657 clk_108MHz: clk-108M {
658 #clock-cells = <0>;
659 compatible = "fixed-clock";
660 clock-frequency = <108000000>;
661 clock-output-names = "108MHz-clock";
665 compatible = "brcm,bcm2712-hvs";
666 reg = <0x10 0x7c580000 0x0 0x1a000>;
667 interrupt-parent = <&disp_intr>;
669 interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof";