Lines Matching +full:brcmstb +full:- +full:reset
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #address-cells = <2>;
8 #size-cells = <2>;
10 interrupt-parent = <&gicv2>;
14 clk_osc: clk-osc {
15 compatible = "fixed-clock";
16 #clock-cells = <0>;
17 clock-output-names = "osc";
18 clock-frequency = <54000000>;
21 clk_vpu: clk-vpu {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
24 clock-frequency = <750000000>;
25 clock-output-names = "vpu-clock";
28 clk_uart: clk-uart {
29 compatible = "fixed-clock";
30 #clock-cells = <0>;
31 clock-frequency = <9216000>;
32 clock-output-names = "uart-clock";
35 clk_emmc2: clk-emmc2 {
36 compatible = "fixed-clock";
37 #clock-cells = <0>;
38 clock-frequency = <200000000>;
39 clock-output-names = "emmc2-clock";
44 #address-cells = <1>;
45 #size-cells = <0>;
47 /* Source for L1 d/i cache-line-size, cache-sets, cache-size
48 …* https://developer.arm.com/documentation/100798/0401/L1-memory-system/About-the-L1-memory-system?…
49 * Source for L2 cache-line-size and cache-sets:
50 …* https://developer.arm.com/documentation/100798/0401/L2-memory-system/About-the-L2-memory-system?…
51 * and for cache-size:
56 compatible = "arm,cortex-a76";
58 enable-method = "psci";
59 d-cache-size = <0x10000>;
60 d-cache-line-size = <64>;
61 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
62 i-cache-size = <0x10000>;
63 i-cache-line-size = <64>;
64 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
65 next-level-cache = <&l2_cache_l0>;
67 l2_cache_l0: l2-cache {
69 cache-size = <0x80000>;
70 cache-line-size = <64>;
71 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
72 cache-level = <2>;
73 cache-unified;
74 next-level-cache = <&l3_cache>;
80 compatible = "arm,cortex-a76";
82 enable-method = "psci";
83 d-cache-size = <0x10000>;
84 d-cache-line-size = <64>;
85 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
86 i-cache-size = <0x10000>;
87 i-cache-line-size = <64>;
88 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
89 next-level-cache = <&l2_cache_l1>;
91 l2_cache_l1: l2-cache {
93 cache-size = <0x80000>;
94 cache-line-size = <64>;
95 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
96 cache-level = <2>;
97 cache-unified;
98 next-level-cache = <&l3_cache>;
104 compatible = "arm,cortex-a76";
106 enable-method = "psci";
107 d-cache-size = <0x10000>;
108 d-cache-line-size = <64>;
109 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
110 i-cache-size = <0x10000>;
111 i-cache-line-size = <64>;
112 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
113 next-level-cache = <&l2_cache_l2>;
115 l2_cache_l2: l2-cache {
117 cache-size = <0x80000>;
118 cache-line-size = <64>;
119 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
120 cache-level = <2>;
121 cache-unified;
122 next-level-cache = <&l3_cache>;
128 compatible = "arm,cortex-a76";
130 enable-method = "psci";
131 d-cache-size = <0x10000>;
132 d-cache-line-size = <64>;
133 d-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
134 i-cache-size = <0x10000>;
135 i-cache-line-size = <64>;
136 i-cache-sets = <256>; // 64KiB(size)/64(line-size)=1024ways/4-way set
137 next-level-cache = <&l2_cache_l3>;
139 l2_cache_l3: l2-cache {
141 cache-size = <0x80000>;
142 cache-line-size = <64>;
143 cache-sets = <1024>; //512KiB(size)/64(line-size)=8192ways/8-way set
144 cache-level = <2>;
145 cache-unified;
146 next-level-cache = <&l3_cache>;
150 /* Source for cache-line-size and cache-sets:
151 * https://developer.arm.com/documentation/100453/0401/L3-cache?lang=en
152 * Source for cache-size:
155 l3_cache: l3-cache {
157 cache-size = <0x200000>;
158 cache-line-size = <64>;
159 cache-sets = <2048>; // 2MiB(size)/64(line-size)=32768ways/16-way set
160 cache-level = <3>;
161 cache-unified;
167 compatible = "arm,psci-1.0", "arm,psci-0.2";
170 rmem: reserved-memory {
172 #address-cells = <2>;
173 #size-cells = <2>;
177 no-map;
181 compatible = "shared-dma-pool";
184 linux,cma-default;
185 alloc-ranges = <0x0 0x00000000 0x0 0x40000000>;
190 compatible = "simple-bus";
192 #address-cells = <1>;
193 #size-cells = <1>;
195 pcie_rescal: reset-controller@119500 {
196 compatible = "brcm,bcm7216-pcie-sata-rescal";
198 #reset-cells = <0>;
202 compatible = "brcm,bcm2712-sdhci",
203 "brcm,sdhci-brcmstb";
206 reg-names = "host", "cfg";
209 clock-names = "sw_sdio";
210 mmc-ddr-3_3v;
213 bcm_reset: reset-controller@1504318 {
214 compatible = "brcm,brcmstb-reset";
216 #reset-cells = <1>;
220 compatible = "brcm,bcm2835-system-timer";
226 clock-frequency = <1000000>;
230 compatible = "brcm,bcm2835-mbox";
233 #mbox-cells = <0>;
241 clock-names = "uartclk", "apb_pclk";
242 arm,primecell-periphid = <0x00341011>;
246 interrupt-controller@7d517000 {
247 compatible = "brcm,bcm7271-l2-intc";
250 interrupt-controller;
251 #interrupt-cells = <1>;
255 compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
257 gpio-controller;
258 #gpio-cells = <2>;
259 brcm,gpio-bank-widths = <17 6>;
260 /* The lack of 'interrupt-controller' property here is intended:
266 gicv2: interrupt-controller@7fff9000 {
267 compatible = "arm,gic-400";
272 interrupt-controller;
273 #interrupt-cells = <3>;
276 aon_intr: interrupt-controller@7d510600 {
277 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
280 interrupt-controller;
281 #interrupt-cells = <1>;
285 compatible = "brcm,bcm2712-pixelvalve0";
291 compatible = "brcm,bcm2712-pixelvalve1";
297 compatible = "brcm,bcm2712-mop";
299 interrupt-parent = <&disp_intr>;
304 compatible = "brcm,bcm2712-moplet";
306 interrupt-parent = <&disp_intr>;
310 disp_intr: interrupt-controller@7c502000 {
311 compatible = "brcm,bcm2711-l2-intc", "brcm,l2-intc";
314 interrupt-controller;
315 #interrupt-cells = <1>;
319 compatible = "brcm,brcm2711-dvp";
322 #clock-cells = <1>;
323 #reset-cells = <1>;
327 compatible = "brcm,brcmstb-i2c";
329 interrupt-parent = <&bsc_irq>;
331 clock-frequency = <97500>;
332 #address-cells = <1>;
333 #size-cells = <0>;
337 compatible = "brcm,brcmstb-i2c";
339 interrupt-parent = <&bsc_irq>;
341 clock-frequency = <97500>;
342 #address-cells = <1>;
343 #size-cells = <0>;
346 bsc_irq: interrupt-controller@7d508380 {
347 compatible = "brcm,bcm7271-l2-intc";
350 interrupt-controller;
351 #interrupt-cells = <1>;
354 main_irq: interrupt-controller@7d508400 {
355 compatible = "brcm,bcm7271-l2-intc";
358 interrupt-controller;
359 #interrupt-cells = <1>;
363 compatible = "brcm,bcm2712-hdmi0";
373 reg-names = "hdmi",
383 interrupt-parent = <&aon_intr>;
386 interrupt-names = "cec-tx", "cec-rx", "cec-low",
387 "hpd-connected", "hpd-removed";
392 compatible = "brcm,bcm2712-hdmi1";
402 reg-names = "hdmi",
412 interrupt-parent = <&aon_intr>;
415 interrupt-names = "cec-tx", "cec-rx", "cec-low",
416 "hpd-connected", "hpd-removed";
422 compatible = "simple-bus";
423 #address-cells = <2>;
424 #size-cells = <2>;
432 dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
439 compatible = "brcm,bcm2712-vc6";
443 compatible = "brcm,bcm2712-pcie";
446 linux,pci-domain = <0>;
447 max-link-speed = <2>;
448 num-lanes = <1>;
449 #address-cells = <3>;
450 #interrupt-cells = <1>;
451 #size-cells = <2>;
452 interrupt-parent = <&gicv2>;
455 interrupt-names = "pcie", "msi";
456 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
457 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
462 reset-names = "rescal", "bridge";
463 msi-controller;
464 msi-parent = <&pcie0>;
467 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
469 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
472 dma-ranges =
473 /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */
480 compatible = "brcm,bcm2712-pcie";
483 linux,pci-domain = <1>;
484 max-link-speed = <2>;
485 num-lanes = <1>;
486 #address-cells = <3>;
487 #interrupt-cells = <1>;
488 #size-cells = <2>;
489 interrupt-parent = <&gicv2>;
492 interrupt-names = "pcie", "msi";
493 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
494 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
499 reset-names = "rescal", "bridge";
500 msi-controller;
501 msi-parent = <&mip1>;
504 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
506 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
509 dma-ranges =
510 /* 64GiB, 64-bit, non-prefetchable at PCIe 10_0000_0000 */
512 /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP1 */
519 compatible = "brcm,bcm2712-pcie";
522 linux,pci-domain = <2>;
523 max-link-speed = <2>;
524 num-lanes = <4>;
525 #address-cells = <3>;
526 #interrupt-cells = <1>;
527 #size-cells = <2>;
528 interrupt-parent = <&gicv2>;
531 interrupt-names = "pcie", "msi";
532 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
533 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
538 reset-names = "rescal", "bridge";
539 msi-controller;
540 msi-parent = <&mip0>;
543 /* ~4GiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
545 /* 12GiB, 64-bit, prefetchable at PCIe 04_0000_0000 */
548 dma-ranges =
549 /* 4MiB, 32-bit, non-prefetchable at PCIe 00_0000_0000 */
551 /* 64GiB, 64-bit, prefetchable at PCIe 10_0000_0000 */
553 /* 4KiB, 64-bit, non-prefetchable at PCIe ff_ffff_f000 MIP0 */
559 mip0: msi-controller@1000130000 {
560 compatible = "brcm,bcm2712-mip";
563 msi-controller;
564 msi-ranges = <&gicv2 GIC_SPI 128 IRQ_TYPE_EDGE_RISING 64>;
565 brcm,msi-offset = <0>;
568 mip1: msi-controller@1000131000 {
569 compatible = "brcm,bcm2712-mip";
572 msi-controller;
573 msi-ranges = <&gicv2 GIC_SPI 247 IRQ_TYPE_EDGE_RISING 8>;
574 brcm,msi-offset = <8>;
579 compatible = "arm,armv8-timer";
592 clk_27MHz: clk-27M {
593 #clock-cells = <0>;
594 compatible = "fixed-clock";
595 clock-frequency = <27000000>;
596 clock-output-names = "27MHz-clock";
599 clk_108MHz: clk-108M {
600 #clock-cells = <0>;
601 compatible = "fixed-clock";
602 clock-frequency = <108000000>;
603 clock-output-names = "108MHz-clock";
607 compatible = "brcm,bcm2712-hvs";
609 interrupt-parent = <&disp_intr>;
611 interrupt-names = "ch0-eof", "ch1-eof", "ch2-eof";