Lines Matching +full:0 +full:x300
16 #clock-cells = <0>;
23 #clock-cells = <0>;
30 #clock-cells = <0>;
37 #clock-cells = <0>;
45 #size-cells = <0>;
54 cpu0: cpu@0 {
57 reg = <0x000>;
59 d-cache-size = <0x10000>;
62 i-cache-size = <0x10000>;
69 cache-size = <0x80000>;
81 reg = <0x100>;
83 d-cache-size = <0x10000>;
86 i-cache-size = <0x10000>;
93 cache-size = <0x80000>;
105 reg = <0x200>;
107 d-cache-size = <0x10000>;
110 i-cache-size = <0x10000>;
117 cache-size = <0x80000>;
129 reg = <0x300>;
131 d-cache-size = <0x10000>;
134 i-cache-size = <0x10000>;
141 cache-size = <0x80000>;
157 cache-size = <0x200000>;
175 atf@0 {
176 reg = <0x0 0x0 0x0 0x80000>;
182 size = <0x0 0x4000000>; /* 64MB */
185 alloc-ranges = <0x0 0x00000000 0x0 0x40000000>;
191 ranges = <0x00000000 0x10 0x00000000 0x80000000>;
197 reg = <0x00119500 0x10>;
198 #reset-cells = <0>;
204 reg = <0x00fff000 0x260>,
205 <0x00fff400 0x200>;
215 reg = <0x01504318 0x30>;
221 reg = <0x7c003000 0x1000>;
231 reg = <0x7c013880 0x40>;
233 #mbox-cells = <0>;
238 reg = <0x7d001000 0x200>;
242 arm,primecell-periphid = <0x00341011>;
248 reg = <0x7d517000 0x10>;
256 reg = <0x7d517c00 0x40>;
268 reg = <0x7fff9000 0x1000>,
269 <0x7fffa000 0x2000>,
270 <0x7fffc000 0x2000>,
271 <0x7fffe000 0x2000>;
278 reg = <0x7d510600 0x30>;
286 reg = <0x7c410000 0x100>;
292 reg = <0x7c411000 0x100>;
298 reg = <0x7c500000 0x28>;
305 reg = <0x7c501000 0x20>;
307 interrupts = <0>;
312 reg = <0x7c502000 0x30>;
320 reg = <0x7c700000 0x10>;
328 reg = <0x7d508200 0x58>;
333 #size-cells = <0>;
338 reg = <0x7d508280 0x58>;
343 #size-cells = <0>;
348 reg = <0x7d508380 0x10>;
356 reg = <0x7d508400 0x10>;
364 reg = <0x7c701400 0x300>,
365 <0x7c701000 0x200>,
366 <0x7c701d00 0x300>,
367 <0x7c702000 0x80>,
368 <0x7c703800 0x200>,
369 <0x7c704000 0x800>,
370 <0x7c700100 0x80>,
371 <0x7d510800 0x100>,
372 <0x7c720000 0x100>;
393 reg = <0x7c706400 0x300>,
394 <0x7c706000 0x200>,
395 <0x7c706d00 0x300>,
396 <0x7c707000 0x80>,
397 <0x7c708800 0x200>,
398 <0x7c709000 0x800>,
399 <0x7c700180 0x80>,
400 <0x7d511000 0x100>,
401 <0x7c720000 0x100>;
426 ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
427 <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
428 <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
429 <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
430 <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
432 dma-ranges = <0x00 0x00000000 0x00 0x00000000 0x10 0x00000000>,
433 <0x10 0x00000000 0x10 0x00000000 0x01 0x00000000>,
434 <0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>,
435 <0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>,
436 <0x1c 0x00000000 0x1c 0x00000000 0x04 0x00000000>;
444 reg = <0x10 0x00100000 0x00 0x9310>;
446 linux,pci-domain = <0>;
456 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
457 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
458 <0 0 0 2 &gicv2 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
459 <0 0 0 3 &gicv2 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
460 <0 0 0 4 &gicv2 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
468 <0x02000000 0x00 0x00000000 0x17 0x00000000 0x00 0xfffffffc>,
470 <0x43000000 0x04 0x00000000 0x14 0x00000000 0x03 0x00000000>;
474 <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>;
481 reg = <0x10 0x00110000 0x00 0x9310>;
493 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
494 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
495 <0 0 0 2 &gicv2 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
496 <0 0 0 3 &gicv2 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
497 <0 0 0 4 &gicv2 GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
505 <0x02000000 0x00 0x00000000 0x1b 0x00000000 0x00 0xfffffffc>,
507 <0x43000000 0x04 0x00000000 0x18 0x00000000 0x03 0x00000000>;
511 <0x03000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>,
513 <0x03000000 0xff 0xfffff000 0x10 0x00131000 0x00 0x00001000>;
520 reg = <0x10 0x00120000 0x00 0x9310>;
532 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
533 interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
534 <0 0 0 2 &gicv2 GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
535 <0 0 0 3 &gicv2 GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
536 <0 0 0 4 &gicv2 GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
544 <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0xfffffffc>,
546 <0x43000000 0x04 0x00000000 0x1c 0x00000000 0x03 0x00000000>;
550 <0x02000000 0x00 0x00000000 0x1f 0x00000000 0x00 0x00400000>,
552 <0x43000000 0x10 0x00000000 0x00 0x00000000 0x10 0x00000000>,
554 <0x03000000 0xff 0xfffff000 0x10 0x00130000 0x00 0x00001000>;
561 reg = <0x10 0x00130000 0x00 0xc0>,
562 <0xff 0xfffff000 0x00 0x1000>;
565 brcm,msi-offset = <0>;
570 reg = <0x10 0x00131000 0x00 0xc0>,
571 <0xff 0xfffff000 0x00 0x1000>;
593 #clock-cells = <0>;
600 #clock-cells = <0>;
608 reg = <0x10 0x7c580000 0x0 0x1a000>;