Lines Matching +full:gic +full:- +full:timer
1 // SPDX-License-Identifier: GPL-2.0
5 * Architecture Envelope Model (AEM) ARMv8-A
11 /dts-v1/;
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include "rtsm_ve-motherboard.dtsi"
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 stdout-path = "serial0:115200n8";
38 #address-cells = <2>;
39 #size-cells = <0>;
45 enable-method = "spin-table";
46 cpu-release-addr = <0x0 0x8000fff8>;
47 next-level-cache = <&L2_0>;
53 enable-method = "spin-table";
54 cpu-release-addr = <0x0 0x8000fff8>;
55 next-level-cache = <&L2_0>;
61 enable-method = "spin-table";
62 cpu-release-addr = <0x0 0x8000fff8>;
63 next-level-cache = <&L2_0>;
69 enable-method = "spin-table";
70 cpu-release-addr = <0x0 0x8000fff8>;
71 next-level-cache = <&L2_0>;
74 L2_0: l2-cache0 {
76 cache-level = <2>;
77 cache-unified;
87 reserved-memory {
88 #address-cells = <2>;
89 #size-cells = <2>;
95 compatible = "shared-dma-pool";
97 no-map;
101 gic: interrupt-controller@2c001000 { label
102 compatible = "arm,gic-400", "arm,cortex-a15-gic";
103 #interrupt-cells = <3>;
104 #address-cells = <0>;
105 interrupt-controller;
113 timer {
114 compatible = "arm,armv8-timer";
119 clock-frequency = <100000000>;
123 compatible = "arm,armv8-pmuv3";
131 compatible = "arm,rtsm-display";
134 remote-endpoint = <&clcd_pads>;
140 #interrupt-cells = <1>;
141 interrupt-map-mask = <0 0 63>;
142 interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
143 <0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
144 <0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
145 <0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
146 <0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
147 <0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
148 <0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
149 <0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
150 <0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
151 <0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
152 <0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
153 <0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
154 <0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
155 <0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
156 <0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
157 <0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
158 <0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
159 <0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
160 <0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
161 <0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
162 <0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
163 <0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
164 <0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
165 <0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
166 <0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
167 <0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
168 <0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
169 <0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
170 <0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
171 <0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
172 <0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
173 <0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
174 <0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
175 <0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
176 <0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
177 <0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
178 <0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
179 <0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
180 <0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
181 <0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
182 <0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
183 <0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
184 <0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;